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* x86: Remove board_early_init_r()Simon Glass2014-11-25-5/+0
| | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-24-0/+2
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| * ARM: Add arch/arm/cpu/armv7/Kconfig with non-secure and virt optionsHans de Goede2014-11-24-0/+2
| | | | | | | | | | | | | | | | | | Add arch/arm/cpu/armv7/Kconfig with non-secure and virt options, this is a preparation patch for adding an env variable to choose between secure / non-secure boot on non-secure boot capable systems, specifically this prepares for adding CONFIG_ARMV7_BOOT_SEC_DEFAULT as a proper Kconfig option. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-24-349/+458
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| * | mx6boards: Fix error handling in board_mmc_init()Fabio Estevam2014-11-24-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Cc: Eric Benard <eric@eukrea.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | nitrogen6x: Fix error handling in board_mmc_init()Fabio Estevam2014-11-24-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Cc: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | ot1200: Fix error handling in board_mmc_init()Fabio Estevam2014-11-24-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | arm: mx6: cm_fx6: implement board specific sata stopNikita Kiryanov2014-11-24-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | Provide board specific implementation for sata stop command for cm_fx6. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de>
| * | gw_ventana: Use the generic spl_sd.cfgFabio Estevam2014-11-24-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gw_ventana can boot from SPI or NAND and both of these interfaces boot from the same 0x400 offset. This means that we could simplify the code and replace the custom gw_ventana.cfg with the generic spl_sd.cfg, as it provides the same boot offset of 0x400. Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx53ard: Fix error handling in board_mmc_init()Fabio Estevam2014-11-21-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx53evk: Fix error handling in board_mmc_init()Fabio Estevam2014-11-21-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx53smd: Fix error handling in board_mmc_init()Fabio Estevam2014-11-21-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6qarm2: Fix error handling in board_mmc_init()Fabio Estevam2014-11-21-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx51evk: Fix error handling in board_mmc_init()Fabio Estevam2014-11-21-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | tbs2910: Fix error handling in board_mmc_init()Soeren Moch2014-11-21-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Based on similar patches by Fabio Estevam for mx6sabresd, mx53loco, wandboard Signed-off-by: Soeren Moch <smoch@web.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | imx: imx6q/dlsabreauto: Add PMIC Pfuze100 supportYe.Li2014-11-20-0/+15
| | | | | | | | | | | | | | | | | | | | | Add the pfuze100 initialization in power_init_board for imx6q/dl sabreauto board. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6sxsabresd: Use the pfuze common init functionYe.Li2014-11-20-41/+7
| | | | | | | | | | | | | | | | | | | | | | | | Modify the pfuze init for mx6sxsabresd to use the shared "pfuze_common_init" function. And move this initialization to power_init_board. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6sabresd: Use the pfuze common init functionYe.Li2014-11-20-43/+9
| | | | | | | | | | | | | | | | | | | | | | | | Modify the pfuze init for mx6sabresd to use the shared "pfuze_common_init" function. And move this initialization to power_init_board. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6sabre common: Factorize the Pfuze init functionYe.Li2014-11-20-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the Pfuze initializations are similar on various mx6 SABRE boards. Factorize the initialization to a common function in file board/freescale/common/pfuze.c. So that all SABRE boards BSP can share the function. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6sxsabresd: Add board support for USDHC2 and USDHC3Ye.Li2014-11-20-5/+94
| | | | | | | | | | | | | | | | | | | | | | | | Add full support for USDHC2, USDHC3, USDHC4 on mx6sx sabresd board. The default boot socket is USDHC4, so the MMC environment device and mmcdev variable are set to this device. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | mx6sabresd: Access SRC_SBMR1 register via structureFabio Estevam2014-11-20-3/+2
| | | | | | | | | | | | | | | | | | | | | In U-boot it is preferred to access the register via structure pointer, so convert it such style. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | tqma6: use imx_ddr_sizeMarkus Niebel2014-11-20-1/+1
| | | | | | | | | | | | Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | tqma6: add warning on failed setup_i2cMarkus Niebel2014-11-20-4/+16
| | | | | | | | | | | | | | | | | | | | | setup_i2c has a return value. Use it to give feedback on error. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | tqma6: add missing includeMarkus Niebel2014-11-20-0/+1
| | | | | | | | | | | | | | | | | | Add include needed to have prototype for board_spi_cs_gpio Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | mx6sabresd: Add mx6sabresd_spl_defconfig to MAINTAINERS entryFabio Estevam2014-11-20-0/+1
| | | | | | | | | | | | | | | | | | | | | Let's add mx6sabresd_spl_defconfig entry into MAINTAINERS, so that we avoid getting a warning that the mx6sabresd_spl is not maintained. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6sxsabresd: Simplify the return value of setup_fec()Fabio Estevam2014-11-20-6/+1
| | | | | | | | | | | | | | | | | | | | | We can simply the return the value from enable_fec_anatop_clock() to make the code smaller and simpler. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6slevk: Simplify the return value of setup_fec()Fabio Estevam2014-11-20-6/+1
| | | | | | | | | | | | | | | | | | | | | We can simply the return the value from enable_fec_anatop_clock() to make the code smaller and simpler. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6sabresd: State that only mx6q is supported in SPLFabio Estevam2014-11-20-4/+2
| | | | | | | | | | | | | | | | | | Make clear that current SPL code only supports the mx6q variant. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx53loco: Fix error handling in board_mmc_init()Fabio Estevam2014-11-20-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | wandboard: Fix error handling in board_mmc_init()Fabio Estevam2014-11-20-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6qsabreauto: Add parallel NOR flash supportFabio Estevam2014-11-20-1/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabreauto boards come with 32 MiB of parallel NOR flash. Add support for it: U-Boot 2015.01-rc1-18107-g1543636-dirty (Nov 14 2014 - 11:11:04) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB Flash: 32 MiB NAND: 0 MiB Due to pin conflict with I2C3, only define configure I2C3 IOMUX when flash is not used. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6: Use a common SPL configuration fileFabio Estevam2014-11-20-44/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Many boards use a minimal .cfg file in the SPL case. Introduce spl_sd.cfg so that we can reuse it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | novena: Move the DCD settings to spl codeFabio Estevam2014-11-20-31/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | gw_ventana: Move the DCD settings to spl codeFabio Estevam2014-11-20-48/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6sabresd: Move the DCD settings to spl codeFabio Estevam2014-11-20-38/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx:mx6sxsabresd fix pfuz probe failedPeng Fan2014-11-20-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PFUZ probe failed with the following msg: " wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=0 wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=1 wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=2 i2c_init_transfer: give up i2c_regs=021a0000 Can't find PMIC:PFUZE100 " board_early_init_f is too early to call i2c related setting, because init_func_i2c is called after board_early_init_f being invoked. Thus move setup_i2c into board_init. Also PFUZ is connected to I2C bus 0, so change "1" -> "0". Using this patch PFUZ can be correctly probed: "PMIC: PFUZE100 ID=0x11" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-3/+25
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * | | dm: tegra: Add platform data for the GPIO driverSimon Glass2014-11-21-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add platform data for the GPIO driver. It doesn't need to contain anything since the GPIO driver will actually use information from the CONFIGs for now. This merely serves to ensure that the GPIO driver is bound. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: at91: Add myself as maintainer for snapper9260Simon Glass2014-11-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The old maintainer has left, so take this over. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: at91: Convert snapper9260 to use driver modelSimon Glass2014-11-21-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert this at91sam9260-based board to use driver model. This should serve as an example for other similar boards. Serial and GPIO are supported so far. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | | Merge git://git.denx.de/u-boot-x86Tom Rini2014-11-24-2/+214
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/x86/cpu/Makefile Signed-off-by: Tom Rini <trini@ti.com>
| * | | | x86: Rename chromebook-x86 to corebootSimon Glass2014-11-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename this vendor since it is intended to be used on any platform where coreboot runs at reset and then loads U-Boot. So far it is only tested on link. When other boards are supported it is likely that we will need to move to multiple board names, all under the 'coreboot' vendor. So while it would be possible to remove the vendor for now, that would be short-sighted. Suggested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: chromebook_link: Enable GPIO supportSimon Glass2014-11-21-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-21-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | | x86: Add chromebook_link boardSimon Glass2014-11-21-0/+70
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | fs: API changes enabling extra parameter to return size of type loff_tSuriyan Ramasami2014-11-23-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sandbox/ext4/fat/generic fs commands do not gracefully deal with files greater than 2GB. Negative values are returned in such cases. To handle this, the fs functions have been modified to take an additional parameter of type "* loff_t" which is then populated. The return value of the fs functions are used only for error conditions. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> [trini: Update board/gdsys/p1022/controlcenterd-id.c, drivers/fpga/zynqpl.c for changes] Signed-off-by: Tom Rini <trini@ti.com>
* | | | fat: Prepare API change for files greater than 2GBSuriyan Ramasami2014-11-23-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the internal FAT functions to use loff_t for offsets. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> [trini: Fix fs/fat/fat.c for min3 updates] Signed-off-by: Tom Rini <trini@ti.com>
* | | | board/esd/common/auto_update.c: Use <flash.h>Tom Rini2014-11-23-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | A number of prototypes here are now found in <flash.h>. use. Signed-off-by: Tom Rini <trini@ti.com>
* | | | kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada2014-11-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some CPUs of some architectures have SOC directories. At present, the build system directly descends into SOC directories from the top Makefile, but it should generally descend into each directory from its parent directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-11-19 23:15:47 +0000