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* zynq: Add support to find bootmodeJagannadha Sutradharudu Teki2014-01-10-0/+25
| | | | | | | | | | | Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* arm64: board support of vexpress_aemv8aDavid Feng2014-01-09-0/+64
| | | | | Signed-off-by: David Feng <fenghua@phytium.com.cn> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* ARM: dra7_evm: read mac address properly from e-fuseMugunthan V N2014-01-07-4/+4
| | | | | | | Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is not working on some boards, modifying the offset to read properly. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* TI:omap3: Drop omap3_zoom2Tom Rini2014-01-07-702/+0
| | | | | | | The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-531/+815
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| * board:trats1:trats2: fix adapter numberPiotr Wilczek2013-12-31-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This fix is necessary after increased by one the number of adapters in s3c24x0 driver. Tested on Trats and Trats2. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * DTS: Add dts support for SMDK5420Rajeshwari Birje2013-12-30-0/+169
| | | | | | | | | | | | | | | | | | | | | | This patch adds dts support for SMDK5420. exynos5.dtsi created is a common file which has the nodes common to both 5420 and 5250. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add base patch for SMDK5420Rajeshwari Birje2013-12-30-0/+224
| | | | | | | | | | | | | | | | | | | | | | Adding the base patch for Exynos based SMDK5420. This shall enable compilation and basic boot support for SMDK5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5: Create a common board fileRajeshwari Birje2013-12-30-527/+418
| | | | | | | | | | | | | | | | | | | | | | Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-353/+794
|\ \ | |/ |/| | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| * mx6sabresd: Fix LVDS width and color formatFabio Estevam2013-12-17-3/+3
| | | | | | | | | | | | | | | | mx6sabresd boards have a 18-bit LVDS data width and the correct color format is RGB666. Suggested-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Allow probing HSYNC, VSYNC and DISP_CLK signalsFabio Estevam2013-12-17-0/+9
| | | | | | | | | | | | | | | | HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging. Configure them as active pins. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ARM: mx53: video: Add IPUv3 LCD support for M53EVKMarek Vasut2013-12-17-0/+73
| | | | | | | | | | | | | | | | This patch adds support for the AMPIRE 800x480 LCD panel that is available for M53EVK. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * MX6 SabreSD: Use readl() to read the CCM_CCGR3 registerLiu Ying2013-12-17-1/+1
| | | | | | | | | | | | | | | | Align with the context to use readl() to read the CCM_CCGR3 register with memory barrier instead of __raw_readl(). Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * udoo: Add SATA support on uDoo Board.Giuseppe Pagano2013-12-17-0/+4
| | | | | | | | | | | | | | | | Add SATA support on uDoo Board. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * nitrogen6x: Move setup_sata to common partGiuseppe Pagano2013-12-17-26/+1
| | | | | | | | | | | | | | | | | | | | Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6 (DQ/DLS): use macros for mux and pad declarationsEric Nelson2013-12-17-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include <asm/arch/mx6-pins.h> with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: Explicitly pass the I2C bus number in pmic_init()Fabio Estevam2013-12-17-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pmic_init() function has the I2C or SPI bus number that is connected to the PMIC. Instead of passing I2C_PMIC, explicitly pass the I2C bus number via I2C_x definition. The motivation for doing this is to avoid people just doing a copy and paste of I2C_PMIC into their board file when another I2C bus is actually used to interface to their PMIC. This also makes more obvious which is the I2C bus connected to the PMIC, without having to search in the source code for the meaning of the 'I2C_PMIC' number. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * udoo: Fix watchdog during kernel boot.Giuseppe Pagano2013-11-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds. To disabled watchdog during kernel boot, WDI pin of that chip needs to be in "high impedance" state. I.mx6 gpio configuration does not contemplate tristate, so pin is set as input in high impedance. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * udoo: Add ethernet support (FEC + Micrel KSZ9031).Giuseppe Pagano2013-11-28-0/+140
| | | | | | | | | | | | | | | | | | | | Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031). Ethernet speed is currently limited to 10/100Mbps. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * udoo: Move and optimize platform register setting.Giuseppe Pagano2013-11-28-0/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Add SPI NOR supportFabio Estevam2013-11-28-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port. Add support for it. This patch allows the SPI NOR flash to be succesfully detected: => sf probe SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Fix wrong colors in LVDS splashFabio Estevam2013-11-28-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently HDMI splash screen is selected by default on mx6sabresd boards. As LVDS is also enabled, this causes incorrect colors to be displayed im the LVDS panel. Fix this by selecting the LVDS panel as the default splash output and only keep HDMI or LVDS turned on at the same time. Acked-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * efikamx: Fix pmic_init() argumentFabio Estevam2013-11-27-1/+1
| | | | | | | | | | | | | | | | | | On efikamx board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx31pdk: Fix pmic_init() argumentFabio Estevam2013-11-27-1/+1
| | | | | | | | | | | | | | | | | | On mx31pdk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx51evk: Fix pmic_init() argumentFabio Estevam2013-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | On mx51evk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * i.MX6DQ/DLS: replace pad names with their Linux kernel equivalentsEric Nelson2013-11-13-303/+303
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * mx6: titanium: Move BSP code to barco board directoryStefan Roese2013-11-13-0/+0
| | | | | | | | | | | | | | | | | | | | | | Since the titanium board is not a Freescale board, move its BSP code from the freescale board directory to the newly created barco board directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Korsgaard <peter.korsgaard@barco.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Peter Korsgaard <peter.korsgaard@barco.com>
| * titanium: Return the error when cpu_eth_init() failsFabio Estevam2013-11-13-1/+1
| | | | | | | | | | | | | | When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
| * wandboard: Return the error when cpu_eth_init() failsFabio Estevam2013-11-13-1/+1
| | | | | | | | | | | | When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * wandboard: Return the error immediately when ipuv3_fb_init() failsFabio Estevam2013-11-13-1/+3
| | | | | | | | | | | | If ipuv3_fb_init() fails, we should return the error immediately. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-18-3/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla2013-12-18-17/+111
| | | | | | | | | | | | | | | | | | | | | | Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
* | ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-18-3/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: mux: Update mux dataLokesh Vutla2013-12-18-2/+20
| | | | | | | | | | | | | | Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG supportSekhar Nori2013-12-18-0/+16
| | | | | | | | | | | | | | | | | | CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the board. These variables are used by findfdt. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43XX: board: add support for reading onboard EEPROMSekhar Nori2013-12-18-0/+78
| | | | | | | | | | | | | | | | Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Adapt to ti_armv7_common.h config fileLokesh Vutla2013-12-18-1/+1
| | | | | | | | | | | | | | Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-30/+23
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| * | arm: pxa: init ethaddr for LP-8x4x using DTSergei Ianovich2013-12-18-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When DT define aliases for etherner0 and ethernet1, U-Boot automatically patched MAC addresses using ethaddr and eth1addr environment variables respectively. Custom initialization is no longer needed. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
| * | arm: pxa: fix LP-8x4x USB supportSergei Ianovich2013-12-18-14/+24
| | | | | | | | | | | | | | | Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
* | | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-0/+569
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| * | | ARM: tegra: Add the Tamonten™ NG Evaluation Carrier boardAlban Bedel2013-12-18-0/+569
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Add support for the new Tamonten™ NG platform from Avionic Design. Currently only I2C, MMC, USB and ethernet have been tested. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-0/+161
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| * | | arm: koelsch: Add support reset functionNobuhiro Iwamatsu2013-12-18-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | | arm: koelsch: Add support EthernetNobuhiro Iwamatsu2013-12-18-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The koelsch board has one sh-ether device. This supports sh-ether. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | arm: lager: Add support reset functionNobuhiro Iwamatsu2013-12-18-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | The lager board uses I2C for reset. ned-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | | arm: lager: Add support EthernetNobuhiro Iwamatsu2013-12-18-0/+70
| |/ / | | | | | | | | | | | | | | | | | | The lager board has one sh-ether device. This supports sh-ether. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | | arm: atmel: at91sam9x5: cleanup cs configure for spiBo Shen2013-12-17-1/+0
|/ / | | | | | | | | | | | | | | | | As the cs for spi is worked in gpio mode, so no need to configure it as peripheral and then configure to gpio. Configure it to gpio directly. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
generated by cgit v1.1 at 2024-12-26 10:49:51 +0000