| Commit message (Collapse) | Author | Age | Lines |
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THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Couple of issues in commit 21a2eb5f. The RAM size is wrong and
max number of DCD is 220.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Add support for i.MX6DQ/DL arm2 LPDDR2 boards.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Current only set VDDARM_IN@1.175V/VDDSOC_IN@1.175V before ldo bypass switch.
So untile ldo bypass switch happened, these voltage setting is set in ldo-enable
mode. But in datasheet, we need 1.15V + 125mV = 1.275V for VDDARM_IN. We need
to downgrade cpufreq to 400Mhz and restore after ldo bypass mode switch.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Correct the wrong setting, otherwise, i2c recovery code will use
the wrong scl pin to recove, and will never recovery successfully.
Signed-off-by: Robin Gong <b38343@freescale.com>
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The BOOTCFG value used by bmode for SABRESD eMMC are actually for SD card.
Fixed the value to correct one.
Signed-off-by: Ye.Li <B37916@freescale.com>
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HWApps team updates iMX6SX 19x19 validation board LPDDR2 script.
This script is JEDEC compliant.
http://compass.freescale.net/livelink/livelink/open/232537085
Update the LPDDR2 settings in DCD and plugin.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Align the keymap with Android rootfs as:
FUNC1 -- > Volume +
FUNC2 -- > Volume -
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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The kernel changes to fix the mmcblk index with USDHC controllers
as below:
mmcblk0 ---> USDHC1
mmcblk1 ---> USDHC2
mmcblk2 ---> USDHC3
mmcblk3 ---> USDHC4
So in u-boot, the "mmcroot" must be updated together.
When booting from SD/MMC device, change the "mmcroot" to
dynamically set according to the boot USDHC controller.
It is the same mechanism as "mmcdev" used for kernel image loading.
Therefore, the uboot, kernel image, dtb and rootfs are required
in same SD/MMC card.
To disable the mmc dynamical detection, set the "mmcautodetect" to "no",
then "mmcroot" and "mmcdev" will not be overwritten.
When booting from other devices which needs to load kernel, dtb and
rootfs from SD/MMC card, their "mmcdev" reset vaule is
CONFIG_SYS_MMC_ENV_DEV and "mmcroot" reset value is CONFIG_MMCROOT.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Update latest DDR3 scirpts for imx6sx SabreSD and 19x19 DDR3 ARM2 board
as provided by board team.
(http://sw-git.freescale.net/cgi-bin/gitweb.cgi?p=ddr-scripts-rel.git)
Signed-off-by: Ye.Li <B37916@freescale.com>
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The NOR flash PC28F00AG18 has 512 of 256KB erase blocks which are
locked after power on reset. Change the 17x17 ARM2 configurations
to match the flash parameters, and enable the CONFIG_SYS_FLASH_PROTECTION
to allow write to the flash.
The EIM-NOR on 17x17 ARM2 board uses MUXed mode. This has less
effort on board rework.
When boot from EIM-NOR, set SW8, SW7, SW5 to all off.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Currently, kernel common regulator framework can't support setting pmic mode
by common DTS, so move the related code to u-boot firstly.
Signed-off-by: Robin Gong <b38343@freescale.com>
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When enabling "CONFIG_SECURE_BOOT", the build broken on iMX6SX platform
due to two problems.
1. The imximage tool in v2014 changes the command name of "SECURE_BOOT"
to "CSF". Must update it in imximage.cfg scripts.
2. The iMX6SX uses "CONFIG_ROM_UNIFIED_SECTIONS", but some HAB API
definitions are not defined and cause compile errors.
(HAB_RVT_REPORT_EVENT_NEW, HAB_RVT_REPORT_STATUS_NEW,
HAB_RVT_AUTHENTICATE_IMAGE_NEW, HAB_RVT_ENTRY_NEW, HAB_RVT_EXIT_NEW)
Signed-off-by: Ye.Li <B37916@freescale.com>
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The eMMC chip on iMX6SX SABRESD board is DNP at default. HW rework is
needed to weld it on the eMMC socket and disconnect SD card slot.
The pins IOMUX of eMMC are different with SD card slot:
1. The eMMC uses 8 data pins, while SD card slot only uses 4 bits.
2. The CD pin used by SD card slot works as a data pin for eMMC.
So adding a new u-boot target "mx6sxsabresd_emmc" for the eMMC support,
rather than using the SD boot configuration.
Signed-off-by: Ye.Li <B37916@freescale.com>
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add clear print log to show pfuze200 or pfuze100 found on mx6qsabresd/
mx6slevk/mx6sx_19x19_arm2 boards.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Enable the "CONFIG_CMD_BMODE" and add BSP support.
"bmode" supports to reboot:
SD4, QSPI2 (SABRESD)
SD2, SD3, eMMC, QSPI2, NAND, SPINOR (17x17 ARM2)
SD1, QSPI2, SPINOR, EIMNOR (19x19 ARM2)
BTW: Board rework is needed on ARM2 for NAND, SPINOR or EIMNOR boot.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Enable the video drivers and MXS LCDIF driver to support the
splash screen on MX6SX SDB and 19x19 ARM2. Add BSP codes for video
parameters and LCDIF/LVDS initialization.
"panel" env is used for selecting the display panel.
Set "panel" env to "Hannstar-XGA" for LVDS display.
Set "panel" env to "MCIMX28LCD" for parallel LCD display.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Update NAND memory layout for match with new mfg tool.
Signed-off-by: Ke Qinghua <qinghua.ke@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add BSP codes to mx6sxsabresd to support android uboot features:
fastboot, booti and recovery
Signed-off-by: Ye.Li <B37916@freescale.com>
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T support M4 boot in 50 ms, kick start M4 at "board_early_init_f"
stage where u-boot passes ARM and architecture initialization.
Add a configuration "CONFIG_SYS_AUXCORE_FASTUP" for this feature
enablement. And a build config "mx6sxsabresd_m4fastup".
Adjust the default M4 image address to 0x78000000 represented by
"CONFIG_SYS_AUXCORE_BOOTDATA".
When M4 fast boot is enabled, RDC should be enabled together and
the QSPI driver must turn off, because M4 is running on QSPI flash
in XIP. Setup this relationship by configurations.
Signed-off-by: Ye.Li <B37916@freescale.com>
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According to the SRS, in the M4 CAN demo, the GPIO group1 will be
shared between A9 and M4. At A9 side, the pins 0, 1, 2, 3 are used.
M4 also uses one pin in its application.
To synchronize the registers setttings of GPIO1, must enable RDC
and RDC semaphore on the GPIO1.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add BSP codes for iMX6SX SABRE SD board to support SD/MMC,
USB, QSPI2 NOR Flash, Ethernet, I2C, PMIC and
M4 command boot(bootaux).
Add board build targets of SABER SD for boot device:
mx6sxsabresd --- SD/MMC
mx6sxsabresd_qspi2 --- QuadSPI2 NOR flash
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add script "imximage_lpddr2.cfg" for DDR controller settings of LPDDR2.
Modify "plugin.S" for LPDDR2.
Add build target for 19x19 LPDDR2 ARM2 board.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add BSP codes for iMX6SX 19x19 DDR3 ARM2 board to support SD/MMC,
USB, QSPI2 NOR Flash, SPI NOR flash, WEIM NOR Flash, Ethernet,
I2C, PMIC and M4 command boot(bootaux).
Some features has conflicts, so can't be enabled at same time:
WEIM-NOR <---> QSPI pin conflict
QSPI <---> SPI-NOR u-boot driver conflict
SPI-NOR <---> SD2 pin conflict
Add board build targets of 19x19 DDR3 ARM2 for boot device:
mx6sx_19x19_ddr3_arm2 --- SD/MMC/eMMC
mx6sx_19x19_ddr3_arm2_spinor --- SPINOR on ECSPI4 CS0
mx6sx_19x19_ddr3_arm2_eimnor --- WEIM NOR flash
mx6sx_19x19_ddr3_arm2_qspi2 --- QuadSPI2 NOR flash
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add BSP codes for iMX6SX 17x17 ARM2 board to support SD/MMC,
USB, QSPI2 NOR Flash, SPI NOR flash, NAND Flash, Ethernet, I2C
,PMIC and M4 command boot (bootaux).
Some features has conflicts, so can't be enabled at same time:
QSPI <---> NAND pin conflict
QSPI <---> SPI-NOR u-boot driver conflict
SPI-NOR <---> SD2 pin conflict
Add board build targets of 17x17 ARM2 for boot device:
mx6sx_17x17_arm2 --- SD/MMC/eMMC
mx6sx_17x17_arm2_spinor --- SPINOR on ECSPI4 CS0
mx6sx_17x17_arm2_nand --- NAND flash
mx6sx_17x17_arm2_qspi2 --- QuadSPI2 NOR flash
Signed-off-by: Ye.Li <B37916@freescale.com>
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iMX6SX has different enet system clocks with iMX6SL, and has two ENET
controllers. So update clocks and soc APIs accordingly to support this
features.
1. Modify the clock API "enable_enet_clock" to enable enet system clock
for enet controllers.
2. Enet RGMII TX clock source may come from external or internal PLL.
By default, use the external phy CLK_25M output as TX clock source.
When using internal PLL as source, the function enable_fec_anatop_clock
must be called to enable clock for each enet controller.
3. Modify the MAC address function "imx_get_mac_from_fuse" to get either
ENET MAC address.
4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz
reference clock.
5. Modify imx6slevk BSP to fit the new APIs.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Sabreauto board has pin conflict (pin EIM_D18) between NOR flash
and i2c3. To enable the USB host, the i2c3 must be used to operate
the max7310 IO expander to output the VBUS power.
As SPINOR is enabled at default, it is impossible to use USB host
at same time. Thus, remove the SYS_USE_SPINOR from sabreauto
configurations to disable SPINOR.
Signed-off-by: Ye.Li <B37916@freescale.com>
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support
Add the android header file "mx6slevkandroid.h" for imx6slevk android support.
Fix header file and pin name problems in BSP codes.
Remove build warning in cmd_fastboot.c
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.
The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.
The patch has been tested on the i.MX6Q and i.MX6DL arm2 board.
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch adds IPUv3 splash screen support for the MX6Q/SDL
Sabreauto platforms. The default display is the Hannstar-XGA
LVDS panel. Users may set the uboot variable 'panel' to be
'HDMI' to switch to use HDMI splash screen. To avoid duplicate
configures on different sabre platforms, this patch moves
the IPUv3 splash screen relevant configures to the head file
'mx6qsabre_common.h'. Also, this patch modifies the condition
to build in EPDC splash screen feature in order to avoid the
build break due to the migration of the IPUv3 splash screen
relevant configures.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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The DC mapping for LVDS666 is different from that for
RGB666. Currently, we set IPU DI pixel format to be
LVDS666 and set LDB data width to be 24bit. This happens
to make the display work normally somehow. But, the two
configurations are wrong and don't match with each other.
This patch corrects the IPU DI output pixel format from
LVDS666 to RGB666 and LDB data width from 24bit to 18bit.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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As the HDMI splash screen feature is not well supported,
we should not set it to be the default display. In case,
users leave the 'panel' uboot environment variable empty
and connect the board with a HDMI monitor, the HDMI detect
funtion will work and enable the HDMI splash screen. So,
this patch disables HDMI detect function so that users
may only explicitly set the 'panel' variable to be 'HDMI'
to use HDMI splash screen.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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-Use the new pins' name for imx6dl.
-Change the read/write to registers by using register structure.
Signed-off-by: Ye.Li <B37916@freescale.com>
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In order to support the secureboot, please turn on the
CONFIG_SECURE_BOOT in
"include/configs/mx6qsabre_common.h" ---- sabreauto or sabresd
"include/configs/mx6slevk.h" ---- imx6slevk
"include/configs/mx6qarm2.h" ---- arm2
By default, the CONFIG_SECURE_BOOT is disabled.
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch add the plugin mode support for imx6slevk board.
In order to enable the plugin mode, please turn on the
CONFIG_USE_PLUGIN in the include/configs/mx6slevk.h
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch add the plugin mode support for imx6dl and imx6solo sabresd.
In order to enable the plugin mode, please turn on the
CONFIG_USE_PLUGIN in the include/configs/mx6qsabre_common.h
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch add the plugin mode support for sabreauto board.
In order to enable the plugin mode, please turn on the
CONFIG_USE_PLUGIN in the include/configs/mx6qsabre_common.h
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch add the plugin mode support for arm2 board.
In order to enable the plugin mode, please turn on the
CONFIG_USE_PLUGIN in the include/configs/mx6qarm2.h
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch adds the SATA support for i.mx6qsabresd and
i.mx6qsabreauto board
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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1. The i2c2 bus is setup twice, remove the duplication.
2. The i2c settings are duplicated in mx6qsabreauto.h and mx6sabre_common.h,
remove it from mx6qsabreauto.h
Signed-off-by: Ye.Li <B37916@freescale.com>
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The CONFIG_SYS_I2C is enabled on i.mx6 boards. So the CONFIG_SYS_I2C_SLAVE becomes
to unused. Remove this setting.
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch update the DDR script to the ddr-scripts-rel.git
based on the top of the following commit:
7cd1c3b Removed the duplicate script files
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add the GPMI nand support to the iMX6 sabreauto:
--Enable the GPMI NAND at default.
--Enable the clocks
--Set the default environment for nand boot
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add the WEIM-NOR support
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch adds the SPI-NOR support for the i.mx6q/dl/solo:sabresd/auto board:
- Support the SPI-NOR function with sf command,
- Support the enviroment from SPI-NOR when CONFIG_SYS_BOOT_SPINOR
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch is to add the i.MX6solo sabreauto support,
The i.MX6solo sabreauto board configuration has the following
difference with i.MX6dl sabreauto:
- DDR bus width: 32bit
- DDR capacity: 1024M
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch is to add the i.MX6DL sabreauto board support.
i.MX6DL sabreauto board share the same design with i.MX6Q
sabreauto board except the SOC difference.
The DDR script has been updated to the v0.2 version from
ddr-scripts-rel.git, the commit based on is:
bfd157a Updated MX6DL and MX6DQ ARD and SabreSD scripts
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Rename the imximage.cfg to mx6q.cfg.
No function change at all.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The i.MX6solo sabre-sd board configuration has the following
difference with i.MX6dl sabre-sd:
- DDR bus width: 32bit
- DDR capacity: 512M
Signed-off-by: Ye.Li <B37916@freescale.com>
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