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* ENGR00210918-1 android: add mx6sl android supportZhang Jiejing2012-05-29-1/+34
| | | | | | | | | | - add android build config for mx6sl_arm2 board. - add gpio support for mx6sl - add boot image support - add android recovery support - add fastboot support, but fastboot cannot transfer file. Signed-off-by Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00209899-1 mx6x: add generic gpio interface.Zhang Jiejing2012-05-21-38/+19
| | | | | | | | | | | | | | | | | | | | | | Add generic gpio interface in uboot. Seems more and more gpio operation invoke in uboot, without RAW register operation, we should use generic gpio interface. you should define the CONFIG_MXC_GPIO use generic gpio interface: gpio_request, gpio_direction_output, gpio_direction_input, gpio_set_value, gpio_get_value, etc. Test on MX6Q, MX6DL. Other MX6X should also define this config. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00180103 MX6 sabreauto: Adjust IPU AXI-id0/1 Qos valueWayne Zou2012-05-16-6/+6
| | | | | | | | | set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7, mx6q use AXI-id0 for IPU display channel, it should has highest priority(bypass), and AXI-id1 for other IPU channel, it has high priority. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00209059 android: refine fastboot and recovery support.imx-android-r13.3Zhang Jiejing2012-05-14-142/+9
| | | | | | | | | | 1. add check asrc register to enter recovery mode, rather then check the file. 2. fix the boot.img can not fastboot flash function. 3. consolidate and cleanup fastboot code. 4. clean up many build warnning message. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00182739 sabresd I2C:add i2c recovery function in board_lateinitRobin Gong2012-05-11-4/+286
| | | | | | | | | | This issue have been found in mx53_smd(ENGR00163704), and found in sabresd if accessing pfuze while system reboot or reset, I2C bus will be blocked even if reboot,then pfuze will be failed to be probed, all device driver which use pfuze regulator will be impacted. In u-boot, we can check the SDA line low or high, if low, generate SCL and STOP signal to tell I2C device release I2C bus. Please check ENGR00163704 Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00182017 mx6dl sabresd I2C: fix build error and support mx6dl_sabresdRobin Gong2012-05-07-1/+1
| | | | | | | | | | | | | | 1.fix build error : mx6q_sabresd.c: In function 'setup_i2c': mx6q_sabresd.c:382: error: expected ')' before ';' token mx6q_sabresd.c:393: error: expected ';' before '}' token mx6q_sabresd.c: In function 'setup_pmic_voltages': mx6q_sabresd.c:399: warning: unused variable 'val' make[1]: *** [mx6q_sabresd.o] Error 1 2.modify mx6dl_sabresd_config to support pfuze on mx6dl sabresd board Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00181348 pfuze sabresd: pfuze support in u-bootRobin Gong2012-05-04-0/+128
| | | | | | add pfuze and I2C support, support cpu internal LDO bypass which can be enabled by CONFIG_MX6_INTER_LDO_BYPASS Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00181337-4 i.mx6 : i.mx6sl: Fix FEC RX CRC ErrorEric Sun2012-05-03-1/+10
| | | | | | | | | | | Since FEC_RX_ER is not connected with PHY(LAN8720A), we need either configure FEC_RX_ER PAD to other mode than FEC_RX_ER, or configure FEC_RX_ER PAD to FEC_RX_ER but need pull it down, otherwise, FEC MAC will report CRC error always. We configure FEC_RX_ER PAD to GPIO mode here and remove the SW hack which ignore the CRC error in fec driver Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00181337-3 i.mx6: i.mx6sl: add initial support for i.mx6sl ARM2 boardEric Sun2012-05-03-0/+1776
| | | | | | | | | | | | | | | | | This patch is to add the initial support for i.mx6sl ARM2 board, the patch does: - implemention of LPDDR2 init script - Plug-in/DCD mode support to do DDR initialization - Debug UART(UART1) support - SPI-NOR(M25P32, 4MB) flash support - FEC support, PHY(LAN8720A, RMII mode) - SD/MMC card support, SD1/SD2/SD3 Signed-off-by: Danny Nold <dannynold@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com> Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00180955 mx6q sabresd snvs TKT104835: fix long press ONOFF failed in u-bootRobin Gong2012-04-26-0/+11
| | | | | | | | | | | Need set Power Supply Glitch to 0x41736166 and clear Power Supply Glitch Detect bit when POR or reboot or power on, otherwise system could not be power off anymore, it will power up auto agian. These steps may be move to ROM code or fix by soc team in the future(PDM ticket number:TKT104835), anyway,u-boot fix the issue firsly. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00180623 fastboot: add fastboot in MX6Q_SABERSD boardsZhang Jiejing2012-04-24-12/+24
| | | | | | | | add fastboot function back in MX6Q_SABERSD board. the MX6DL_SABERSD have usb init related issue which will keep RESET, but left as later developement. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00179762: i.MX6: print the SOC revision correctlyJason Liu2012-04-18-3/+10
| | | | | | | | | | For example: The soc rev on i.mx6dl rev 1.0 not print correctly: CPU: Freescale i.MX 6 family 0.0V at 792 MHz This patch help u-boot print out the SOC revision correctly: CPU: Freescale i.MX6 family TO1.0 at 792 MHz Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179013 : MX6Solo/Quad : SABREAUTO: Add Parallel NOR SupportPrabhu Sundararaj2012-04-13-4/+127
| | | | | | | | | | | | | -Added u-boot config CONFIG_CMD_WEIMNOR for MX6Solo/Quad SABREAUTO to support WEIM NOR. - CONFIG_FLASH_HEADER_OFFSET is 0x1000 for WEIM NOR. -SPI NOR and WEIM NOR has pin conflicts, either one can be enabled. - mx6q_sabreauto_config, mx6solo_sabreauto_config configured default for SPI NOR. -In order to enable the read/write commands and to boot from WEIM NOR, need to enable the CONFIG_CMD_WEIMNOR. This will disable SPI-NOR Signed-off-by: Prabhu Sundararaj <b36876@freescale.com>
* ENGR00179000 i.mx6q/dl: sabresd: Add the splash screen supportJason Liu2012-04-13-102/+17
| | | | | | | | | | | | | | | | | | | | This patch will add the splash screen support for the i.mx6q/dl splash screen support. In order to enable the splash screen, you need make sure the following env variable has been set correctly: splashimage=0x30000000 splashpos=m,m lvds_num=0 The splash screen is default OFF, to enable it, please add: on i.mx6dq sabresd platform: define CONFIG_SPLASH_SCREEN in include/configs/mx6q_sabresd.h or on i.mx6dl sabresd platform: define CONFIG_SPLASH_SCREEN in include/configs/mx6dl_sabresd.h Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179150 MX6Q_ARM2 HAB Boot : avoid uImage authentication on un-fused chipEric Sun2012-04-09-23/+81
| | | | | | | | | Before running authentication on uImage in DDR, u-boot first check if SEC_CONFIG[1] (OTP_CFG5[1]) is burned. If so, it means the chip is in secure configuration, the authentication continues; if not, the chip in not in secure configuration, just bypass the authentication Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176537 mx6qsabreauto: i2c3_sda route settingAdrian Alonso2012-04-05-2/+24
| | | | | | | | | | * In RevB boards a steer logic circuit enables the route path of I2C3_SDA signal and is controlled by EIM_A24__GPIO_5_4 pad. * Configure GPIO_5_4 as as output and enable steer logic circuit. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00139223-1 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 1)Eric Sun2012-04-01-2/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first stage of High Assurance Boot (HAB) is the authentication of U-boot. A CST tool is used to generate the CSF data, which include public key, certificate and instruction of authentication process. Then it is attached to the original u-boot.bin The IVT should be modified to contain a pointer to the CSF data. The original u-boot.bin is with size between 0x27000 to 0x28000. For convinence, we first extend the u-boot.bin to 0x2F000 (with fill 0xFF). Then concatenate it with the CSF data. The combined image is again extend to a fixed length (0x31000), which is used as the IVT size parameter. The new memory layout is as the following. U-Boot Image +-------------+ | Blank | |-------------| 0x400 | IVT |-----------------------+ |-------------| | | | | | | | | | | |Remaining UB | | CSF pointer | | | | | | | | | |-------------| | | | | | Fill Data | | | | | |-------------| 0x2F000 <-------------+ | | | CSF Data | | | |-------------| | | | Fill Data | | | +-------------+ 0x31000 HAB APIs are ROM implemented, the entry table is located in a fixed location in the ROM. We export them so that during the HAB we can have some information about the secure boot process. For convinience some wrapper API is implemented based on the HAB APIs. - get_hab_status : used to dump information of authentication result - authenticate_image : used by u-boot to authenticate uImage For security hardware to function, CAAM related clock (CG0[4~6]) must be open. They are default closed in the original U-boot. "hab_caam_clock_enable" and "hab_caam_clock_disable" are created to open and close these clock gates. The generation of CSF data is not in the scope of this patch. CST tool will be used for this purpose. The procedure will be introduced in another document. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176834-4 - [imx]:add macro define to include chip head fileFugang Duan2012-03-31-1/+3
| | | | | | | - Different chip will include different head file, so add macro define to limit the use range. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00178558 mx6solo sabreauto: integrate DDR3 script V1.1Lily Zhang2012-03-30-95/+99
| | | | | | | | | This patch is used to integrate DDR3 script V1.1 of mx6solo sabreauto MX6DL_init_DDR3_400MHZ_32bit_sabre_1_1.inc under http://compass.freescale.net/livelink/livelink?func=ll&objid =225128962&objAction=browse&sort=name Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00177954 mx6solo sabreauto: remove MMDC1 settingrel_imx_3.0.15_12.03.00Lily Zhang2012-03-26-44/+39
| | | | | | | Remove MMDC1 setting from DDR script of mx6solo sabreauto if it's not used. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00177783: i.mx6dl: sabresd revB: update DD3 init scriptJason Liu2012-03-23-38/+41
| | | | | | | | | Update the DDR3 script on i.mx6dl SabreSD revB board, the script got from: http://wiki.freescale.net/download/attachments/33954617/MX6DL_init_DDR3 _400MHz_64bit_1_2_For_SD_RevB.inc?version=1&modificationDate=1332495827000 Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00176837-2 - imx6 sabreauto : add i2c3 support for revb board.Fugang Duan2012-03-22-4/+8
| | | | | | - Add i2c3_SDA iomux config for the change of signal traces. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176837-1 - imx6 sabreauto : add net support for revb boards.Fugang Duan2012-03-22-11/+28
| | | | | | | - In imx6 sabreauto board REVB Ethernet phy adopt AR8031. Add phy init rework. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00177244 - imx6 : Use common fsl_sys_rev to check board reversionFugang Duan2012-03-20-54/+7
| | | | | | | | | - Use fsl_sys_rev to check Sebreauto board reversion. - Add macro define for expedient print the board and chip name. mx6_chip_name() mx6_board_rev_name() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-3 - i.MX6DL sabresd : DDR init script updateFugang Duan2012-03-20-10/+10
| | | | | | | | | | | Use the ddr init script “MX6DL_init_DDR3_400MHz_64bit_1.2.inc” for SD revB with Rigel mounted, and update the calibration parameters (write leveling, DQS gating, read delay, write delay), which is located at: http://compass.freescale.net/livelink/livelink?func=ll& objid=225128962&objAction=browse&sort=name Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-2 - i.MX6DL sabresd: board bringupFugang Duan2012-03-20-24/+299
| | | | | | | | | | | | | The serial of patches adds the initial support for mx6dl sabra sd board: - DDR3 400MHz@64bit, 1G, 256M*4 - SD/MMC basic operations - Add PIN/IOMUX support for mmx6dl sabresd. - Ethernet is ok for 100/1000Mbps. - OTP fuse Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-1 - [imx6] : add fsl_system_rev to check chip and board.Fugang Duan2012-03-20-0/+116
| | | | | | | | | | | | | | | - Add fsl_system_rev to distinguish chip ID and board reversion. - Add some api: mx6_chip_is_dq() mx6_chip_is_dl() mx6_chip_is_solo() mx6_chip_is_sololite() mx6_board_is_reva() mx6_board_is_revb() mx6_board_is_revc() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176347-9 fec : increase wait time for phy linkFugang Duan2012-03-13-17/+0
| | | | | | | | | | | | | | - remove the excrescent code in enet_board_init function. - KSZ9021 phy auto-negotiation in mx6solo sabreauto RevA is used to establish link with the remote hub or switch. In general, the negotiation time is about 3-5 senconds But connecting to Gbps hub, the time is range from 8s to 15s. So, changing the MAX link waiting time to 20s. According to repetitious tests, solo ARD ethernet is ok in 100Mbps environment. It is not stable in 1000Mbps mode. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176347-6 mx6solo sabreauto: remove build warningLily Zhang2012-03-13-2/+5
| | | | | | | | | | Remove the following build warning: mx6q_sabreauto.c: In function 'enet_board_init': mx6q_sabreauto.c:999: warning: unused variable 'reg' mx6q_sabreauto.c: At top level: mx6q_sabreauto.c:921: warning: 'phy_read' defined but not used Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-5 mx6solo sabreauto: set system_revLily Zhang2012-03-13-11/+55
| | | | | | | | | | | | | | | | | Add set_system_rev function. The layout of system_rev is: bit 0-7: Chip Revision ID. Read from Anatop register bit 8-11: Board Revision ID. Read from fuse OCOTP_GP1[15:8] 1: RevA Board 0: RevB board, Unknown board bit 12-19: Chip Silicon ID. Read from Anatop register 0x63: i.MX 6Dual/Quad 0x61: i.MX 6Solo/DualLite board_is_rev(system_rev,BOARD_REV_1) can be used to distinguish RevB board. board_is_rev(system_rev,BOARD_REV_2) is for RevA board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-3 mx6solo sabreauto: add board supportLily Zhang2012-03-13-28/+162
| | | | | | | | - Add PIN/IOMUX support for mx6solo sabreauto board - Remove GPIO_9 codes because GPIO_9 is not the backlight - change system_rev as 0x610000 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-2 mx6solo sabreauto: add DDR3 supportLily Zhang2012-03-13-2/+109
| | | | | | | | Add DDR3 script (400MHz@32 bit) in mx6solo sabre auto board. MX6Solo_DDR3_400MHZ_32bit.inc was delivered on Mar 7, 2012 by Fan Chongbin-B32609 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176235 mx6 ARD: Add splash screen supportLily Zhang2012-03-06-6/+6
| | | | | | | | | | | | | | | | | | | This patch adds splash screen support for MX6 ARD. Changes: - Configure GPIO_3 as I2C3_SCL - Change MAX7310 I2C address as 0x30 - Enable LVDS power Usage: 1. To enable splash screen by default, define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2. Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176186 mx6dq ARD: add MFG tool supportLily Zhang2012-03-06-8/+1
| | | | | | Add MFG tool support for i.MX6DQ ARD board Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00175981-1 mx53 smd: add CPU 1.2GHz configurationLily Zhang2012-03-02-1/+12
| | | | | | | | | CONFIG_CPU_1_2G is used to enable 1.2GHz@1.3V. To enable 1.2GHz by default, enable CONFIG_CPU_1_2G into config file. For example, uncomment CONFIG_CPU_1_2G in mx53_smd.h or mx53_smd_android.h. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00175117 [MX6DL LPDDR2 Board] Apply Initializtion script and enable U-BootEric Sun2012-02-29-1/+306
| | | | | | | | | | | | | | | | | Apply script "Mx6DL_init_LPDDR2_400MHz_Micron_1.1.inc" in IVT, make U-boot work for the LPDDR2 Board. The Make target name for the new board is "MX6DL_ARM2_LPDDR2_CONFIG" The script is provided by Chen Wei - B26879 for a quick bring up, which don't have a corresponding compass link. It is uploaded to CR ticket page for reference. Originally for MX6DL DDR3 board, "CONFIG_MX6DL" is defined. It is used by "board/freescale/mx6q_arm2/flash_header.S" to select the correct IVT. Since MX6DL LPDDR2 board also define this macro, for distiguish purpose, another 2 macros "CONFIG_MX6DL_DDR3", "CONFIG_MX6DL_LDPPR2" are defined Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00175091 MX6Q_SABRESD: android: add recovery checkZhang Jiejing2012-02-27-39/+37
| | | | | | | | define a new macro to show which mmc bus was main storage in recovery check, only check the main storage /cache partition. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00174536-1 booti: add booti command support.Zhang Jiejing2012-02-27-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support booti command which can boot from a boot.img boot.img is a zImage + ramdisk.img + bootargs + boot addr which include these info can be used to avoid mis match between kernel and ramdisk, also can avoid commit to chagne default bootargs. For example: > booti mmc1 command will read the boot.img from 1M offset, and then parser the bootargs and ramdisk then do the boot from that zImage. > booti mmc1 recovery will going to read the recovery's partition no and offset and boot from recovery image. this recovery image also a zImage + ramdisk bootargs: if uboot have define a env var 'bootargs', booti command will use this bootargs as kernel cmdline if you want use boot.img 's bootargs, just type: > setenv bootargs in uboot to clear the bootargs in uboot env. our default uboot env will be NULL in config file. also, android use boot.img to support OTA. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00174326 MX6Q_SABRESD: add android related function and config.Zhang Jiejing2012-02-15-0/+162
| | | | | | | | | | enable mfg profile. enable recovery mode. mx6q_sabresd board's usb otg have HW issue, disable it in android profile. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00174104-1: Add conditional CONFIG to fix build breakTerry Lv2012-02-13-0/+9
| | | | | | | | | | | Add CONFIG_MXC_FEC macro to fec init code. Add CONFIG_VIDEO_MX5 to ipu init code. Change temperature function as static. For in iram boot, FEC configs is not needed, those FEC init code will cause build errors. These changes can reduce image size. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00174155: i.mx6sdl: add 32bit DDR support on ARM2 boardJason Liu2012-02-09-0/+5
| | | | | | | | | | | The 32bit DDR script got from the following link: http://compass.freescale.net/livelink/livelink/225194568/ MX6DL_init_DDR3_400MHZ_32bit_1.0.inc.txt?func=doc.Fetch&nodeid=225194568 The DDR hw connection on the ARM2 board is 64bit wire, but we can make it use as 32bit, the side effect is that DDR access size will reduce to the half Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00174055: i.mx6dl: ddr: update ddr script to 400M_64bit_v1.1Jason Liu2012-02-09-14/+14
| | | | | | | | | The script we get from the following link: http://compass.freescale.net/livelink/livelink/225193471/MX6DL_init_ DDR3_400MHz_64bit_1.1.inc.txt?func=doc.Fetch&nodeid=225193471 Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00173966-4: ARM2: add initial support for i.mx6sdlJason Liu2012-02-07-26/+170
| | | | | | | | | | | | | | | | | This patch add the initial support for i.mx6dl ARM2 board -SD/MMC basic -DDR 400Mhz, -FEC,basic Due to i.mx6dl shares the same board with i.mx6q on ARM2, the most common code should be the same as the i.mx6q ARM2 So, no need to create one seperate board file for i.mx6dl. But We can't simply resue anything from the board file since the i.mx6dl iomux is changed and thus we have to deal with the difference between i.mx6q and i.mx6dl for the pad setting part. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00173966-3: ARM2: i.mx6dl: add the DDR scriptJason Liu2012-02-07-3/+133
| | | | | | | | | integrate DDR script http://compass.freescale.net/livelink/ livelink/225147268/rigel_temp.inc.txt?func=doc.Fetch &nodeid=225147268 Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00172343 Add suport for i.MX 6Q Sabre Smart DeviceNancy Chen2012-01-24-0/+1370
| | | | | | | | Add suport for i.MX 6Quad SABRE Smart Device. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com> Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
* ENGR00171622 - FEC : workaround for Gb enet in sabrelite board.Fugang Duan2012-01-11-3/+3
| | | | | | | | Micrel phy KSZ9021 Gb speed cannot work well in i.MX6 sabrelite board. Advertise phy is not 1000Base-T capable, and enet can work well at 100Mbps mode in 1000M environment(1G cable & 1G hub). Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00171115 add fec support in mx6q sabreauto boardHake Huang2011-12-31-36/+25
| | | | | | | | | | Add fec support for sabreauto board Need hardware rework: 1. Add R450 10.0k 2. Remove R1105 1k 3. short Pin 1,2 of u516, will impact CAN1 Signed-off-by: Hake Huang <b20222@freescale.com>
* ENGR00171008 MX6Q/MFGTOOL : disable the workaround for MFGTOOLHuang Shijie2011-12-28-7/+0
| | | | | | Disable the uboot workaround. It will crash the MFGTOOL. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00163697 - FEC : Adjust MX53 Network stream throughput.Fugang Duan2011-12-20-0/+550
| | | | | | | | | | | | | | | | | | | | | - When the system is very busy(such as play 1080p streaming in local) the WIFI & FEC performance were very low. - Enable the patch in uboot for WIFI and FEC performance: If WIFI connect to PORT2, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT2 If WIFI connect to port3, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT3 - The solution of the patch: I. Changing M4IF dynamic jump value to zero, which can guarantee FEC the high rate of accessing bus. II. Increase Master 4 priority for FEC. Increase Master 2 and AHBMAX priority for WIFI. - Test result: i.MX53 FEC bandwidth (1080p streaming playback in local): 47.1 Mbits/sec. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00170516 Enable the master mode for ENET PHY on MX6 SabreliteMahesh Mahadevan2011-12-16-2/+2
| | | | | | Fix the ENET PHY settings on MX6 Sabre-lite to enable Master mode Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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