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* ENGR00161133: Add spi-nor support for mx6qTerry Lv2011-11-01-0/+68
| | | | | | Add spi-nor support for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00161004 MX6Q Uboot Rename sabreauto to arm2 boardAnish Trivedi2011-10-28-10/+14
| | | | | | | | | Sabreauto is an inaccurate name for the Armadillo2 board that this code is actually meant for. So, replaced "sabreauto" in folder names, file names, configs, and code with "arm2". Created a new machine id for ARM2 board. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139221 USDHC Add SDXC UHS-I supportAnish Trivedi2011-10-27-4/+9
| | | | | | | Modified MMC library for UHS-I command sequence Added support to USDHC driver for UHS-I Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00160514: clean up compiler warning for mx6qTerry Lv2011-10-26-2/+3
| | | | | | Clean up compiler warning. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00160399 Added support for the MX6Q Sabre-lite boardMahesh Mahadevan2011-10-25-6/+1140
| | | | | | Includes support for uSDHC read, write, FEC, SPI-NOR etc. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00156934: Update mx35 AIPS max dbg m3if esdctl settingsTerry Lv2011-10-18-18/+32
| | | | | | | This patch is to fix mx35 TVIN flicker issue. It will change AIPS, M3IF, MAX, DBG and esdctl settings. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00156930: Update MX35 DDR2 scriptsTerry Lv2011-10-18-69/+414
| | | | | | | | | | Update MX35 DDR2 scripts for that when enabling 256MB, the CSD1 is not stable. 1. Add CSD1 configs to support 256M RAM. 2. Add mx35 TO2 256M RAM configs. 3. Update DDR init code in lowlevel_init.S for external boot. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139279-3 MX6Q: invalidate the D-CACHEHuang Shijie2011-10-14-0/+37
| | | | | | | | | | | The USB boot mode does not invalidate the D-CACHE, so the uboot will DEAD when it tries to invalidate the random data in the cache line. The MMC boot will do the MMU init which will do the D-CACHE invalidation. So the MMC boot will ok in the boot procedure. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00159845 [MX6]lpddr2 board, put MMDC into power saving modeAnson Huang2011-10-13-2/+10
| | | | | | | | For lpddr2 board. 1. Put mmdc into power saving mode; 2. Do the necessary setting for AXI cache and IPU Qos. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00159696 [MX6]Enable lpddr2 boardAnson Huang2011-10-11-0/+169
| | | | | | | And new config to enable lpddr2 board with H9TKNNN4KDMPQR-NDM chip. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00158184 mx53 smd: use highest value for unknown board revision valueWayne Zou2011-09-26-1/+4
| | | | | | mx53 smd: use highest value for unknown board revision value Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00157538 remove VDIG_PLL setting in plug-in codeLily Zhang2011-09-23-20/+0
| | | | | | | | According to the datasheet, VDIG_PLL needs to be increased to 1.3v for TO2.0. This operation has been done in the low_level_init.S. Remove the duplicated code here. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00155569 mc34708: change global reset time as 4s of LOCO and PCBARobin Gong2011-09-19-0/+22
| | | | | | reduce the time of global reset to 4s in the boards of loco and pcba Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00156389: turn off child clocks before reconfigure perclk_rootTerry Lv2011-09-13-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. Certain steps are required to reconfigure perclk_root. If don't follow these steps, GPT timer may stop and the kernel stops at " "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00156098 mx53_smd/mx53_loco: DA9053 I2C SDA stuck low issue on bootupWayne Zou2011-09-06-2/+204
| | | | | | | | | | | | | | | | For DA9053 I2C SDA stuck low issue: the I2C block in DA9053 may not correctly receive a Power On Reset and device is in unknown state during start-up. The only way to get the chip into known state before any communication with the Chip via I2C is to dummy clock the I2C and bring it in a state where I2C can communicate. Dialog suggested to provide 9 clock on SCL. Dialog don't know the exact reason for the fault and assume it is because some random noise or spurious behaviour. This has to been done in host platform specific I2C driver during start-up when the I2C is being configured at platform level to supply with dummy 9 clock on SCL. Dialog I2C driver has no control to provide dummy 9 clock on SCL. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-2/+275
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHzTerry Lv2011-09-01-6/+42
| | | | | | | | 1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155279: Change ESDCTL_0x82228080 to ESDCTL_0x82226080 for mx35Terry Lv2011-09-01-3/+4
| | | | | | | | | | In mx35, when testing TVIN, the screen will flick. We find that flickers will get better when using ESDCTL_0x82226080 against ESDCTL_0x82228080 for register SCDCTL0. The origin value ESDCTL_0x82228080 in lowlevel_init.S will be called in external boot which will reduce the bandwidth. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155739: mx53 evk mmu wrong mapped two csd slotsTerry Lv2011-09-01-10/+4
| | | | | | | mx53 evk mmu wrong mapped two csd slots. Actually evk only has one slot. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154666-2: Align u-boot mmc command with communityTerry Lv2011-09-01-5/+5
| | | | | | Trivial change to remove build warnings. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155284 mx53_smd: move I2C access to board_init_late for system hang issueWayne Zou2011-08-31-9/+12
| | | | | | | | | | | | MX53 SMD hangs if reset many times with lower possibility. If doing I2C access in early time, I2C may cause system hangs. So moving I2C access to late phase to make system hang issue disappear. QA Test result: QA raised 6 full rounds of CTS one-round test Totally ran for 6 rounds about 27 hours, reboot for 56*6=336 times, no reboot failure occurred. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00155472 mx53_loco: support both of RevA and RevB in ubootRobin Gong2011-08-29-4/+18
| | | | | | to fix we should amend systemrev in uboot, add new board RevB for it Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00154672: Change to use rom plugins for mx53 boardsTerry Lv2011-08-29-465/+889
| | | | | | | | | | | | | 1. As customer required, we change to use rom plugins for mx53 boards. Tested pass with latest mfg tools. 2. Update DDR3 script based on MX53_TO2_DDR3_LCB_SMD_ARDb_v2.inc. Got from http://compass.freescale.net/livelink/livelink?func=ll &objId=221058910&objAction=browse&viewType=1. 3. Fix a tiny build error in mx53_smd.c. This error will happen when building mx53_smd_mfg. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155240 mx53_smd: Fix a bug that hangs on printf() in board_initWayne Zou2011-08-23-5/+1
| | | | | | remove printf() because serial interface is not ready in board_init() Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00155133: Add sata support for imx6Terry Lv2011-08-22-0/+64
| | | | | | Init clocks, phy and pll for sata. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00151255 mx53 QS: Enable VUSB_2V5Lily Zhang2011-08-22-0/+15
| | | | | | | | | Kernel stops at USB driver initialization if suspending, resuming and resetting the board. It's because VUSB_2V5 voltage is disabled after suspend. Need to re-enable it mannually into U-boot Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00155156 [MX6]Clean up debug info in ubootAnson Huang2011-08-22-2/+1
| | | | | | | | 1. ENET don't need to enable ENET pll clock; 2. Enable cpu debug clock in case of using JTAG; 3. Clean up some debug info during bring up. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00155138 mx53_smd/mx53_loco: Add i2c retry to fix DA9053 i2c NAK issueWayne Zou2011-08-22-3/+20
| | | | | | | | | when board boots up, during the iMX53 SOC does DA9053 Read/Write operation, it writes slave address and wait for ACK . Instead of ACK PMIC sends NAK. A workaround fix is provided as a part of retries to fix I2C NAK for very first access. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00155018 mx53_pcba: update Ripley AUX input to 950mA and charge currentWayne Zou2011-08-19-2/+3
| | | | | | | set Ripley AUX input current limit to 950mA and set charge termination current to 400mA Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00154924 [MX6]Disable some clocks in ubootAnson Huang2011-08-17-2/+7
| | | | | | | | | | | We should disabel some clocks in uboot to save power, or when we download from enet to boot up kernel, the power consumption could be up 800mA@5V, may damage the chip. After apply it, we can save more then 200mA@5V. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00154762 mx53_pcba: update Ripley/mc34708 USB/AUX charger settingsWayne Zou2011-08-12-4/+13
| | | | | | update Ripley USB and AUX/DC charger settings for pcba revB board Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00154468 mx53 pcba: Add DC-IN power supply support for revB boardWayne Zou2011-08-08-1/+9
| | | | | | | | Add DC-IN power supply support for revB board when booting from EMMC. set both AUX&USB current limit to 1.5A for Ripley 2.1 only Change CC current to 950mA Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00154400 mx53 pcba: bringup update for RevB boardXinyu Chen2011-08-05-13/+16
| | | | | | | | | Update DDR DCD configuration Open all the clocks during boot Change CV voltage to 4.2V Signed-off-by: Weihua Zou <wayne.zou@freescale.com> Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00153761 imx6q ipuv3: improve display qualityrel_imx_2.6.38_11.08.00Jason Chen2011-07-27-2/+8
| | | | | | | | | to avoid ipu starvation issue. 1. enable IPU AXI cache in uboot 2. set Qos to 7 for IPU to highest priority in uboot. 3. set AXI id to 0 for high priority IDMA channel in linux. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00153526 mx53 pcba: add pcba board revB support in ubootXinyu Chen2011-07-27-0/+1156
| | | | | | | | | | | | | | | Add new machine type for pcba. Add UART, I2C, SD/MMC, PMIC, DDR initial support. Add MFG tool support. Add support for MC34708 on revB pcba board. Update VDDGP setting on MC34708 PMIC for revB board. Close unused clock, for fastboot it will enable usb_phy usb_oh3 clock by itself, still need to verify this work or not when revB bootup. Signed-off-by: Wayne Zou <b36644@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00153597 [MX6]Enbale MMDC low powerAnson Huang2011-07-25-3/+4
| | | | | | | Enable auto self-refresh of MMDC to save power when memory idle. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00143438 [MX50 RD3]DCDC_3V15 GPIO changeAnson Huang2011-07-22-2/+2
| | | | | | | Change DCDC_3V15's GPIO setting for REV-D. Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit 28a8e166c6a8fa001325f88ef06e5a81f6ed82a9)
* ENGR00151310 mx53 smd: force warm reset as cold resetLily Zhang2011-07-22-0/+9
| | | | | | | | | | This patch is used to support watchdog timeout in SMD RevA, RevB board. 1. Revert "ENGR00143469 mx53 smd: pull down GPIO_9 to reset the board". 2. Force warm reset as cold reset. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00151695 mx53 ddr3: update ESDREF and MR0Lily Zhang2011-07-21-9/+9
| | | | | | | | | | | Updated mx53 ddr3 script according to MX53_TO2_DDR3_LCB_SMD_ARDb_v1.inc from Michael J Kjar on July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This chagned write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00153394 mx50 rd3: make SDHC1 as default boot device for androidXinyu Chen2011-07-20-0/+6
| | | | | | | Drop NAND/SPI boot support. Enable fastboot. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00152755 MX6 Switch DRAM init script from plugin to DCD for emmc fastbootAnish Trivedi2011-07-06-263/+140
| | | | | | | | | | | | | | | | | ROM requires DCD table instead of plugin to initialize DRAM if emmc fastboot mode is to be used. Therefore, switched the DRAM script from plugin to DCD table. The DCD table created is based on the following RVD script: Arik_init_DDR3_528MHz_002.inc found at http://compass.freescale.net/livelink/livelink?func=ll&objId=222928845 When fastboot mode is used by ROM, the MMC_BOOT register of USDHC does not get reset when RSTA bit is set by uboot driver. Therefore, need to write 0 to it manually during driver init. This brings USDHC out of fastboot mode, allowing normal communication with emmc to proceed in uboot. Changed comments for DLL delay to be more accurate. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139206 MX6 USDHC eMMC 4.4 supportAnish Trivedi2011-07-05-4/+17
| | | | | | | | | | | New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00152439: MX51: PLL workaround should be implemented only for PLL1Ranjani Vaidyanathan2011-07-01-2/+15
| | | | | | Make sure the PLL workaround is done only for PLL1. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00139198: iMX61 uBoot add ENET supportZeng Zhaoming2011-06-27-1/+3
| | | | | | | | | | | | | | | | Add ENET and AR8031 PHY support to uboot. To make it works on sabreauto, need do following changes: 1. rework phy to output 125M clock from CLK_25M signal, and the 125M clock input to SoC as reference clock to generate RGMII_TXC clock. 2. Enable TXC delay in PHY debug register. 3. set ENET working in RMII mode. 4. set ENET working at 1000M or 100M/10M. 5. set ENET TX fifo to maximum to avoid underrun error. 6. force AR8031 PHY working at 100M Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00144424 MX6: enable uboot for ARM2(SABREAUTO) CPU boardAnson Huang2011-06-24-0/+961
| | | | | | | | | | | | | Use 528M DDR script Disable L2 cache because rom enable L2 cache when use plug-in Fix usdhc pad settings Remove mac address hardcode Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00151966: MX51 - Apply SW workaround for the PLL1 unlock HW issue.Ranjani Vaidyanathan2011-06-22-10/+43
| | | | | | | | | | | | | | | | | | | | | | Apply the following SW workaround to fix the PLL unlock issue. 1.Move all the clock sources which are currently running on PLL1 from PLL1 to PLL2 2.Clear AREN bit in PLL1 (to avoid restart during MFN change) 3.Program the PLL1 to the next settings: a. MFI = 8 b. MFD = 179 c. MFN = 180 d. PLM = 1 4.Manually restart the PLL1 5.Wait to PLL1 to lock 6.Reprogram the PLL1 to the next settings: a. MFI = 60, others keep same 7.Load the MFN 8.Wait for LDREQ and delay ~4.6us 9.Switch the clocks which were previously moved from PLL1 to PLL2 back to PLL1 Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00151892 MX50: Workaround to prevent PLL1 from losing lockAnish Trivedi2011-06-21-24/+59
| | | | | | | | | | | | | | | PLL1 workaround to prevent it from losing lock: (1) Disable AREN bit to avoid PLL1 restart during MFN change (2) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179, PDF = 0 (3) Manual restart PLL1 (4) Wait PLL1 lock (5) Set PLL1 to 800Mhz with only change MFN to 60, others keep (6) Set LDREQ bit to load new MFN (7) Poll on LDREQ bit for MFN update to be completed (8) Delay at least 4 us to avoid PLL1 instability window (9) Switch ARM back to PLL1 Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00151187 MX53 SMD: Kernal stopped Usb driver after reseting in stop modeWayne Zou2011-06-10-1/+14
| | | | | | | After reseting in stop mode, the VUSB_2V5 voltage is disable by pmic. It needs to be enable manually in u-boot. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00144224: MX53: Add MMU mapping for all peripheralsTerry Lv2011-06-09-36/+84
| | | | | | | Not all peripherals are mapped in MMU. Thus we add those missed mapped area. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00144389 mx53 QS Ripley: change VCC from 1.35V to 1.3V QS Ripley boardWayne Zou2011-06-01-2/+2
| | | | | | Change VCC from 1.35V to 1.3V QS Ripley board Signed-off-by: Wayne Zou <b36644@freescale.com>
generated by cgit v1.1 at 2024-11-22 01:30:18 +0000