summaryrefslogtreecommitdiff
path: root/board
Commit message (Collapse)AuthorAgeLines
* ENGR00140537 mx53: update vddgp according to new data sheetZhou Jingyu2011-03-23-0/+33
| | | | | | mx53: update vddgp according to new data sheet Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140982 MX53 Increase VDDGP to 1.25V for 1 GHzAnish Trivedi2011-03-22-6/+6
| | | | | | | | MX53 TO 2.0 requires 1.25V for VDDGP instead of 1.2V in order for the core to operate at 1 GHz. Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140872 Add MX50 RD3 SupportRobby Cai2011-03-22-10/+60
| | | | | | | | Assembled With new PMIC chip - MC34708 (Ripley), and new SPI NOR - M25P32 as well. Add new config file for RD3. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00140825: Add mx53 to2.1 chip id recognitionTerry2011-03-20-4/+17
| | | | | | Add mx53 to2.1 chip id recognition. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140692 Update for DDR3-based MX53 SABRE Auto boardsMahesh Mahadevan2011-03-16-4/+102
| | | | | | | Added a new config file, the DDR setup is similar to the MX53 Quick Start & MX53 SABRE-Tablet ref design boards. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00139747: Read fuse to distinguish between mx53 revA and revBTerry Lv2011-03-02-7/+36
| | | | | | | | | Read fuse to distinguish between mx53 revA and revB. Now SoC efuse is used for board id. Thus we now check fuse value for board rev and id. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139924 mx53 smd &loco: set bootup vdd GP to 1.2vZhou Jingyu2011-03-01-0/+6
| | | | | | set bootup vdd GP to 1.2v for mx53 smd &loco Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00138689 MX50 Update LPDDR2 script to use more optimized settingsAnish Trivedi2011-01-31-315/+42
| | | | | | | | | | | | | | | | New LPDDR2 initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_LPDDR2_266MHz.inc v7, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Also removed ARM2 LPDDR2 init section since the settings for that board are the same as the RDP (EVK). Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00138635 MX50 Update mDDR script to use more optimized settingsAnish Trivedi2011-01-28-55/+55
| | | | | | | | | | | | | New mDDR (LPDDR1) initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_LPDDR1_200MHz.inc v4, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00138148 MX53 TO2.0 EVK: change the default core as 1GHZLily Zhang2011-01-18-9/+18
| | | | | | | Change the default core frequency as 1GHZ for MX53 TO2.0 EVK board Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00138040-3 Protect splashimage related stuffs by configLiu Ying2011-01-17-3/+5
| | | | | | | This patch protects splashimge related stuffs by config option for mx51 bbg, mx53 ard and mx53 smd. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137552 MX53: increase VDDGP as 1.2V for 1GHZLily Zhang2011-01-15-3/+30
| | | | | | | | | The norminal voltage of VDDGP for 1GHZ is 1.2V in MX53 TO2.0 datasheet (RevD). So set the CPU frequency as 800MHZ firstly since VDDGP is 1.1V after power on. After increasing VDDGP as 1.2V, increase CPU as 1GHZ. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137894-6 MX53 SMD:Support splashimageLiu Ying2011-01-14-1/+127
| | | | | | | | | | | | | | This patch supports to use pwm wave to control backlight. The pwm rate is 20KHz and the pwm duty is 50%. Only lvds panel is supported. Use 'lvds_num' env variable to choose to use lvds0 or lvds1. However, only lvds1 is tested as the lvds cable cannot be plugged into lvds0 connector. Note that you need to add 'splashimage' env variable to set the memory address of the bmp image. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-5 MX53 ARD:Support splashimageLiu Ying2011-01-14-0/+207
| | | | | | | | | | | This patch supports to use pwm wave to control backlight. The pwm rate is 200Hz and the pwm duty is 50%. Use 'lvds_num' env variable to choose to use lvds0 or lvds1. Note that you need to add 'splashimage' env variable to set the memory address of the bmp image. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-4 IPUv3 FB: IPUv3 FB driver enhancementLiu Ying2011-01-14-3/+6
| | | | | | | | 1) Change MX51 related function names to IPUv3 related names. 2) Change MX51 related comments to IPUv3 related comments. 3) Do not set panel_info.cmap to be NULL pointer. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137791 MX53: Update for MFG toolLily Zhang2011-01-11-8/+1
| | | | | | | | - Add MFG tool support for MX53 SMD and MX53 LOCO boards - Update mx53 ARD MFG defconfig to pass compile Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137766 BBG splashimage:Allocate cmap for panel_infoLiu Ying2011-01-10-1/+10
| | | | | | | This patch allocates cmap for panel_info, otherwise, cmap_base in common/lcd.c will be NULL pointer. Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00137604: Change PLL4 to 455MHz for mx53Terry Lv2011-01-07-4/+24
| | | | | | | Required by display to set ldb. We need to set PLL4 to 455MHz. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137642 MX53 Uboot Align DDR3 script for Loco and SMD boardsAnish Trivedi2011-01-05-4/+4
| | | | | | | | | | | | | Changed the value of one register, offset 0x88, of the ESDCTL controller to match the official script for the boards, entitled "MX53_TO2_DDR3_LCB.inc", found at http://compass.freescale.net/livelink/livelink/221435668/ MX53_TO2_DDR3_LCB.inc.txt?func=doc.Fetch&nodeid=221435668 The register value sets read delay lines. The change is minor. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00137497-2 MX53: Add LOCO board supportLily Zhang2010-12-30-0/+1202
| | | | | | | | | | | Add MX53 LOCO board support The following functions are tested in the board: - Micro SD boot - MMC/SD read/write. - clk command - fuse command Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00136075 MX53: Add SMD board supportLily Zhang2010-12-30-0/+1236
| | | | | | | | | | | | | | | | | | | | | | | Add MX53 SMD support: - Use DDR3 script for SMD board from Mike Kjar: "Rita_init_LCB_CMOS.inc" - Set the default CPU core frequency as 1GHZ. The following functions are tested on SMD board: - SD/MMC boot, read, write via SDHC1 - eMMC4.4 boot, read, write via SDHC3. - SATA boot, read, write. To support SATA boot via internal clock, please ensure the fuse "SATA_ALT_CLK_REF" was blown. - FEC - UART - clk command - iim command Signed-off-by: Liu Ying <b17645@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137410 MX53 split board files into different foldersLily Zhang2010-12-29-332/+1439
| | | | | | Split different MX53 board files into different folder. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137372 MX53: Switch back to use DCD and update DDR scriptsLily Zhang2010-12-28-444/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. This patch is used to switch back to use DCD for flash header instead of plug-in. This change request is due to the following reasons: 1) U-boot community doesn't accept current plug-in solution when upstreaming. 2) Plug-in isn't supported by MX53 ROM serial download mode. No effective workaround is found now. To use the same code base to support normal U-Boot and MFG tool better, adopt DCD solution firstly. 3) Current MX53 DDR scripts don't exceed the length limitation of DCD. For MX53 TO2.0 EVK/ARM2 board, raise DDR frequency to 400MHZ after VCC and VDDA voltages are raised as 1.3V. Since ARM2 CPU2 board share the same script with EVK, delete ARM2 CPU2 config files. ARM2 CPU2 board can share the same bootloader with EVK. 2. Update MX53 DDR2 scripts for TO1.0/TO2.0 EVK/ARD/ARM2 boards The script "MX53_TO2_DDR2_EVK_ARD.inc" is located under http://compass.freescale.net/livelink/livelink? func=ll&objId=221058910&objAction=browse&viewType=1 This script is published by ATX and FIL team on Dec 16th, 2010 3. Update MX53 ARM2 CPU3 DDR3 script "MX53_TO2_DDR3_CPU3.inc" under the same compass folder Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137211 U-Boot MX5x: Incorrect GPL license header on filesXinyu Chen2010-12-22-7/+28
| | | | | | Correct the GPL license Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00137214 MX50: Turn on ZQ calib config by default and fix hang problemRobby Cai2010-12-21-24/+22
| | | | | | | | 1) Turn on ZQ calib config by default in uboot. 2) Remove one problematic statement which can cause hang issue 3) Change comment style from ; to // Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00134068 MX51 BBG:Support CLAA WVGA splashimageLiu Ying2010-12-16-0/+30262
| | | | | | | | | | | 1) IOMUX/backlight support for CLAA WVGA LCD panel. 2) Add video mode for CLAA WVGA LCD panel. 3) Support IPU di1 interface for framebuffer. 4) Enhance IPU driver. 5) Add freescale 600x400 8BPP BMP logo. Signed-off-by: Terry Lv <R65388@freescale.com> Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00133727: uart outputs messy code when kernel starts on mx51Terry Lv2010-12-14-3/+3
| | | | | | | uart outputs messy code when kernel starts on mx51. Change uart clock to use pll2 as source clock. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00136038: Remove config CONFIG_EMMC_DDR_MODETerry Lv2010-12-10-1/+7
| | | | | | | | | 1. As we can check DDR dynamically, remove CONFIG_EMMC_DDR_MODE in mmc.c. 2. Add config CONFIG_EMMC_DDR_PORT_DETECT config for some boards that only some board support DDR. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00136170 MX50 Add ZQ calibration revision for TO1.1Robby Cai2010-12-09-62/+138
| | | | | | | | | | | | | | | | | | | | All type of DDRs will be affected. ddr script is available here: http://compass.freescale.net/livelink/livelink/open/218722501 Two key points: 1. LPDDR2 ZQ calibration is different from mDDR/DDR2, fixed in this version(they're same before). 2. TO1.1 ZQ calibration is _NOT_ compatible with TO1.0. U-Boot default config is for TO1.1. Please switch off CONFIG_ZQ_CALIB option if compile for TO1.0. Other fixes: 1. Change drive strength to 0x00200000 for all ddr types. 2. Add missed config for IOMUXC_SW_PAD_CTL_PAD_DRAM_OPEN and IOMUXC_SW_PAD_CTL_PAD_DRAM_OPENFB. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00136081 DDR script update for MX53 TO2 ARDDinh Nguyen2010-12-08-46/+41
| | | | | | | | | Updated DDR2 script for ARD board from Mike Kjar: "mx53_init_TO2_DDR2_ARD_test.inc". Tested on TO1 and TO2 ARD. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
* ENGR00136042 Add ZQ calib config and update script for DDR2Robby Cai2010-12-08-2/+2
| | | | | | | | script v2: http://compass.freescale.net/livelink/livelink/219931536/ Codex_DDR2_266MHz.inc.txt?func=doc.Fetch&nodeid=219931536 Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00133744: Merge mx50_arm2 to mx50_rdpTerry Lv2010-12-01-2968/+1365
| | | | | | Merge mx50_arm2 to mx50_rdp. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00025557: MX50 Add ZQ calibration support for TO1.1.1.Terry Lv2010-12-01-79/+487
| | | | | | | MX50 Add ZQ calibration support for TO1.1.1. This need to be enabled by CONFIG_ZQ_CALIB. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR12345678 Change ddr write delay in the PHYRobby Cai2010-12-01-16/+16
| | | | | | | | | | Total 5 registers: 0x1400023c/244/24c/254/25c: from 0x000a1401 to 0x000a0b01 Without this patch, kernel on RDP board with Elpida DDR is not able to boot, or not stable. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00133437 MX50 Uboot support for TO 1.1.1 precodeAnish Trivedi2010-12-01-7/+42
| | | | | | | Precoding: Update DDR configuration plugin to check SI Rev and change ROM addresses as needed. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00133124: Add nand support for mx50 rdpTerry Lv2010-11-18-5/+213
| | | | | | Add nand support for mx50 rdp. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00133689 MX51: set MC13892 charge output voltage as 4.2VLily Zhang2010-11-17-3/+20
| | | | | | | | This patch is to set MC13892 charge regulator output voltage as 4.2V. It fixes a typo error for chip check and makes TO3 VCC and VDDA voltages keep sync with the spec. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132909 MX53 Uboot: Support for TO2Anish Trivedi2010-11-15-323/+467
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support new DDR script entitled "Rita_TO2_init_DDR2_CPU2_CMOS_TEST_CAL_v1.inc" for DDR2 boards including MX53 EVK, ARD, and ARM2 CPU2. These new settings did not apply to TO1. Therefore, changed the DCD for these boards to a plugin so that TO1 and TO2 can both be supported using conditional execution of new DDR settings. During bootup on TO2, DDR frequency is required to be below 400 MHz. Therefore, BOOT_CFG2[4] must be set to enable DDR at 333 MHz in ROM on all boards. Uboot determines silicon version and for TO2 boosts the VCC and VDDA voltages to 1.3V, after which the DDR frequency is also increased to 400 MHz. This requirement meant that uboot does not calibrate PLL2 anymore until the voltage is increased. Removed the calibration from lowlevel_init.S and from all mx53 include/configs files. Also required that during config_periph_clk(), only CBCMR register is touched to set source PLL. Other changes to CBCDR were removed. Switching to PLL2 bypass clk during reprogram was also removed. All these changes are required to increase DDR frequency to 400 MHz. DDR2 CPU2 board with TO1 requires the following hw cfgs: JP3 populated, and J8 set to 2-3. For DDR2 CPU2 board with TO2, both these jumpers should be depopulated. ARM2 CPU3 (with DDR3) DDR configurations were not changed. TO1 and TO2 can run well using existing DDR3 script. However, DCD was converted to plugin to align with other boards. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00133530 plug-in support mfgtools and sb_loaderFrank Li2010-11-09-18/+24
| | | | | | | mfgtools and sb_loader can download plug-in and run plug-in to initilize DRAM. Signed-off-by: Frank Li <frank.li@freescale.com>
* ENGR00133049 Support nand flash for MX28Frank Li2010-11-04-2/+36
| | | | | | | Support nand basic read/write in MX28 u-boot. Signed-off-by: Frank Li <frank.li@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00132957 mfg-tool: should add stop usb operation for mx50 rdpPeter Chen2010-10-26-0/+7
| | | | | | | It should add stop usb operation for mx50 rdp, otherwise, the usb enumeration at kernel will be very slow Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00132758 correct NFC_CLK definitionLily Zhang2010-10-19-1/+1
| | | | | | | | This patch is used to fix the issue caused by ENGR00132709. NFC_CLK definition should be used in cmd_clk interface. MXC_NFC_CLK should be used as internal clock name. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132709 MX53: add "clk nfc" command supportLily Zhang2010-10-18-0/+7
| | | | | | | | Add "clk nfc" command support. Limit NFC MAX clock as 34MHZ to be compatible with some old NAND flashes. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132617 MX53: add NAND supportLily Zhang2010-10-17-0/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support for MX53 EVK and ARD. Need to use kobs-ng to flash U-Boot on MX53 TO1. Because MX51 TO1 ROM doesn't support bi swap solution and kernel enable bi swap, Must enable "ignore bad block" option when flashing U-Boot. The step is as following: echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad Since default configuration stores environment into SD card and U-Boot uses get_mmc_env_devno (Read SBMR register) to get MMC/SD slot information, you must insert SD card to bottom SD slot to get/store environment if you are using NAND boot on MX53 EVK. You must config boot dip setting well when doing NAND boot. For example, if you are using NAND 29F32G080AA NAND chip on MX53 EVK, you can set boot dips as the following for NAND boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on. Other dips are off. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132526 MX50 RDP Update to latest LPDDR2 scriptAnish Trivedi2010-10-13-21/+52
| | | | | | | | | | | | | | | Update uboot LPDDR2 init code with the following changes from latest script (v04) from Marek Xu: http://compass.freescale.net/doc/220496654/Codex_LPDDR2_266MHz.inc.txt 1. Driver strength changed to 0x00180000 from 0x00200000 2. Memory type value changed to 0x04000000 from 0x02000000 3. New ZQ calibration entries with delay between load PU/PD and clear 4. Register at memory location 0x14000024 changed to 0x0048D005 from 0x0048EB05 Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00131936 MX5X corrent mx53_evk mx51_BBG android default env settingZhang Jiejing2010-09-26-4/+2
| | | | | | | | | | | | | | This change make a bootable default setting of MX53 EVK and MX51 BBG board, the old default setting is too old to boot android system up. Also add the recovery command in the env strings, if you want to boot to recovery mode with mx53_evk, you can just : > run bootcmd_android_recovery This command will boot android into recovery mode. Also fix MX51 can't see UI in recovery mode. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00131691 MX50 RDP UbootAnish Trivedi2010-09-21-0/+1590
| | | | | | | | | | Add support for building uboot for MX50 reference design platform: 1) LPDDR2 init script (v0.3 from Mike Kjar, dated 9/14) 2) iomux 3) new board file and machine id for RDP 4) Updates for iram boot on RDP Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00131779: Use serial_mxc as uart driver for all platformsTerry Lv2010-09-21-0/+2
| | | | | | Use serial_mxc as uart driver for all platforms. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00131705-4 MX53: fix typo error for recoveryLily Zhang2010-09-21-1/+1
| | | | | | Fix typo error for MX53 recovery mode. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00131705-2 Add MX53 ARD supportLily Zhang2010-09-20-6/+336
| | | | | | | | | | | Add MX53 Automotive Reference Board (ARD) support 1. Add DDR2 initialization script 2. Add external ethernet support 3. Update PIN settings for UART, I2C, SDHC etc Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com>
generated by cgit v1.1 at 2024-11-22 17:16:22 +0000