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* ppc4xx: Rework of 4xx serial driver (2)Stefan Roese2007-10-31-316/+40
| | | | | | | | | | Change all linker scripts to reference the changed driver name 4xx_uart.o. Note: In most cased all these explicit referencing of these object files in the linker scripts is not neccessary. Only for manually embedded environment into the U-Boot image, which is not done is most cases. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial AMCC Makalu 405EX supportStefan Roese2007-10-31-0/+1228
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xxStefan Roese2007-10-31-17/+11
| | | | | | | | | | This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix size setup in Kilauea DDR2 init routineStefan Roese2007-10-31-26/+26
| | | | | | | | | The size was initilized wrong. Instead of 256MB, the DDR2 controller was setup to 512MB. Now the correct values is used. This patch also does a little cleanup and adds a comment here. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint modeStefan Roese2007-10-31-104/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable device tree support (fdt) on Kilauea per defaultStefan Roese2007-10-31-0/+14
| | | | | | | | | | | | | This patch enables the fdt support on the AMCC Kilauea eval board. Additionally now EBC ranges fdt fixup is included to support NOR FLASH mapping via the Linux physmap_of driver. This Kilauea port now support booting arch/ppc and arch/powerpc Linux kernels. The default environment "net_nfs" is for arch/ppc and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc support will be removed. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix small merge problems with CPCI440 and Acadia boardsStefan Roese2007-10-31-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial AMCC Kilauea 405EX supportStefan Roese2007-10-31-0/+1125
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platformsStefan Roese2007-10-31-6/+6
| | | | | | | | These files were introduced with the IBM 405GP but are currently used on all 4xx PPC platforms. So the name doesn't match the content anymore. This patch renames the files to 4xx_pci.c/h. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)Stefan Roese2007-10-31-14/+8
| | | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)Stefan Roese2007-10-31-8/+7
| | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'motionpro_ng' of /home/tur/git/u-bootWolfgang Denk2007-10-24-0/+6
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| * Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration.Bartlomiej Sieka2007-10-23-0/+6
| | | | | | | | | | | | | | | | Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay register must be written a value of 0x00000004 as the first step of the SDRAM contorller configuration. Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
* | TQM5200S: fix commands for STK52xx base board because of missing SM501 ↵Martin Krause2007-10-24-7/+12
| | | | | | | | | | | | | | | | | | | | | | grafic controller Some commands for the STK52xx base board try to access the SM501 grafic controller. But the TQM5200S has no grafic controller (only the TQM5200 and the TQM5200B have). This patch deactivates the commands accessing the SM501 for the TQM5200S. Signed-off-by: Martin Krause <martin.krause@tqs.de>
* | xsengine: Fix no partition type specified, use DOS as defaultJean-Christophe PLAGNIOL-VILLARD2007-10-24-2/+2
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Fix warning differ in signedness in board/innokom/innokom.cJean-Christophe PLAGNIOL-VILLARD2007-10-23-1/+1
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | fix pxa255_idp boardMarcel Ziswiler2007-10-23-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pxa255_idp being an old unmaintained board showed several issues: 1. CONFIG_INIT_CRITICAL was still defined. 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined. 3. Symbol flash_addr was undeclared. 4. The boards lowlevel_init function was still called memsetup. 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000. 6. Using -march=armv5 instead of -march=armv5te resulted in lots of 'target CPU does not support interworking' warnings on recent compilers. 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as indexes rather than the register definitions from the pxa-regs header file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to avoid any ambiguities. 8. There were several redefinition warnings concerning ICMR, OSMR3, OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file. 9. The board configuration file was rather outdated. 10. The part header file defined the vendor, product and revision arrays as unsigned chars instead of just chars in the block_dev_desc_t structure. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-tq-groupWolfgang Denk2007-10-21-7/+9
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| * TQM8xx: Fix CAN timing.Jens Gehrlein2007-10-15-7/+9
| | | | | | | | Signed-off-by: Martin Krause <martin.krause@tqs.de>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2007-10-18-1/+7
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| * | ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap commandStefan Roese2007-10-18-1/+7
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | mpc83xx: pq-mds-pib.c typo errorTony Li2007-10-18-13/+13
|/ / | | | | | | | | | | | | Correct to val8 from val. Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | ppc4xx: Fix bug in I2C bootstrap values for Sequoia/RainierStefan Roese2007-10-15-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & YosemiteStefan Roese2007-10-15-5/+9
|/ | | | | | | | | | | The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix warning differ in signedness in board/mpl/vcma9/vcma9.cWolfgang Denk2007-10-13-2/+2
| | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-avr32Wolfgang Denk2007-10-13-4/+0
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| * AVR32: Initialize bi_flash* in board_init_rHaavard Skinnemoen2007-10-06-4/+0
| | | | | | | | | | | | | | | | | | | | | | The ATSTK1000-specific flash driver intializes bi_flashstart, bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI driver, don't. Initialize these in board_init_r instead so that things will still be set up correctly when we switch to the CFI driver. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-armWolfgang Denk2007-10-13-1/+1
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| * \ Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-10-04-5/+12
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| * | Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-09-18-57/+46
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| * \ \ Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-09-11-3/+6
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| * \ \ \ Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-09-10-21/+46
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| * \ \ \ \ Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-09-07-27/+921
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| * | | | | | Changed API name to coloured_led.hPeter Pearse2007-09-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed code using deprecated ifdef CONFIG_BOOTBINFUNC Tidied other cpu/arm920t/start.S code
| * | | | | | Add coloured led interface for ARM boards.Peter Pearse2007-09-04-45/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use it in cpu/arm920t/start.S to indicate U-Boot code has been entered.
| * | | | | | Move include/led.h to board/at91rm9200dkPeter Pearse2007-09-04-0/+45
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* | | | | | | CM5200: Fix missing null-termination in hostname manipulation codeBartlomiej Sieka2007-10-05-0/+1
| |_|_|_|_|/ |/| | | | | | | | | | | | | | | | | Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
* | | | | | ppc4xx: Coding style cleanupStefan Roese2007-10-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | Program EPLD to force full duplex mode for PHY.Grzegorz Bernacki2007-10-02-5/+12
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* | | | | TQM8xx[LM]: Fix broken environment alignment.Wolfgang Denk2007-09-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With recent toolchains, the environment sectors were no longer aligned to sector boundaries. The reason was a combination of two bugs: 1) common/environment.c assumed that CONFIG_TQM8xxL would be defined for all TQM8xxL and TQM8xxM boards. But "include/common.h", where this gets defined, is not included here (and cannot be included without causing lots of problems). Added a new #define CFG_USE_PPCENV for all boards which really want to put the environment is a ".ppcenv" section. 2) The linker scripts just include environment.o, silently assuming that the objects in that file are really in the order in which they are coded in the C file, i. e. "environment" first, then "redundand_environment", and "env_size" last. However, current toolchains (GCC-4.x) reorder the objects, causing the environment data not to start on a flash sector boundary: Instead of: we got: 40008000 T environment 40008000 T env_size 4000c000 T redundand_environment 40008004 T redundand_environment 40010000 T env_size 4000c004 T environment Note: this patch fixes just the first part, and cures the alignment problem by making sure that "env_size" gets placed correctly. However, we still have a potential issue because primary and redundant environment sectors are actually swapped, i. e. we have now: 40008000 T redundand_environment 4000c000 T environment 40010000 T env_size This shall be fixed in the next version. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | ColdFire: fix build error becasue of bad type of mii_init()Liew Tsi Chung-r5aahp2007-09-15-6/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
* | | | | ColdFire: Fix build error caused by pixis.cLiew Tsi Chung-r5aahp2007-09-15-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the #include <asm/cache.h> inside the #ifdef CONFIG_FSL_PIXIS. Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
* | | | | Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as globalWolfgang Denk2007-09-15-35/+27
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | Make DECLARE_GLOBAL_DATA_PTR global for DaVinciDirk Behme2007-09-15-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As discussed in [1], DECLARE_GLOBAL_DATA_PTR has to be global and not function local. Signed-off-by: Dirk Behme <dirk.behme@gmail.com> [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805
* | | | | cm5200: Fix a typo introduced by afaac86fe2948ac84cd9a12bbed883b3c683e7d9Bartlomiej Sieka2007-09-13-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marian Balakowicz <m8@semihalf.com>
* | | | | Fix memory corruption problem on STX GP3 SSA Board.Wolfgang Denk2007-09-12-1/+4
| |_|_|/ |/| | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot toGrzegorz Bernacki2007-09-11-3/+6
| |_|/ |/| | | | | | | | | | | | | | scan on second pci bus. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* | | Merge with /home/raj/git/u-boot#440SPe_PCIe_fixesWolfgang Denk2007-09-08-20/+46
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| * | | [PPC440SPe] PCIe environment settings for Katmai and YuccaGrzegorz Bernacki2007-09-07-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
| * | | [PPC440SPe] Improve PCIe configuration space accessGrzegorz Bernacki2007-09-07-20/+22
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
generated by cgit v1.1 at 2024-11-23 22:27:56 +0000