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* ENGR00229456 Support for 64bit DDR configuration for ARDAlejandro Sierra2012-10-12-0/+117
| | | | | | | Added support for 64bit DDR configuration on DL chip. On ARD platform Signed-off-by: Alejandro Sierra <b18039@freescale.com>
* ENGR00228238 i.mx6/i.mx6dl: sabresd: add solo-ddr32bit supportJason Liu2012-10-11-2/+125
| | | | | | | | This patch adds the solo-ddr32bit config support. The DDR script got from: http://compass.freescale.net/livelink/livelink/227589697/ MX6DL_init_DDR3_400MHz_32bit_For_SD_1.0.inc.txt?func=doc.Fetch&nodeid=227589697 Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00223797-1 MX6 SabreSD:Align IPU related clocks with kernelLiu Ying2012-09-27-18/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aligns IPU related clocks with imx_3.0.35(_android) kernel setting to support smooth transition from uboot splash screen to kernel stage. The IPU related clock trees are: 1) MX6DQ SabreSD: ipu1_clk -- osc_clk(24M)->pll2_528_bus_main_clk(528M)->periph_clk(528M) ->mmdc_ch0_axi_clk(528M)->ipu1_clk(264M) ipu1_pixel_clk_x -- osc_clk(24M)->pll2_528_bus_main_clk(528M)-> pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)-> ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M) 2) MX6DL SabreSD: ipu1_clk -- osc_clk(24M)->pll3_usb_otg_main_clk(480M)-> pll3_pfd_540M(540M)->ipu1_clk(270M) ipu1_pixel_clk_x -- osc_clk(24M)->pll2_528_bus_main_clk(528M)-> pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)-> ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M) Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00223794 MX6 SabreSD:Enable LVDS panel pwm backlightLiu Ying2012-09-27-14/+13
| | | | | | | | | | | | | This patch enables pwm backlight for LVDS panel and stops using gpio backlight to align with kernel to avoid unstable backlight when booting into kernel, as kernel usually uses pwm backlight instead of gpio backlight. Following items are done to support this: 1) Add PWM1 and PWM2 controller base addresses. 2) Change PIN SD1_DAT3 mux from GPIO to PWM1_PWMO. 3) Set default backlight density to 50%. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00222170: Add mx6sl_evk_android_config for mx6sl evk boardLiGang2012-09-06-1/+18
| | | | | | | - mx6sl_evk_android.h is a new file, copied from mx6sl_arm2_android.h - set default sdio port as mmc1 Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00219316-2: mx6q sabreauto enable lvds backlight by defaultAdrian Alonso2012-08-29-25/+32
| | | | | | | | | | | | | * Enable lvds backlight by default, configure io_expander A to enable backlight. * As weimnor_d18, spinor_d18, i2c3_sda share the pad MX6Q_PAD_EIM_D18 if wiemnor or spinor is enabled it overrides i2c3 settings and kernel fails to configure io_expander causing read/write errors. * This commit allows a default configuration on control lines behind io_expander A. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00221013 MX6 SabreSD:Disable LVDS panel CABC functionLiu Ying2012-08-28-0/+38
| | | | | | | | | This patch sets CABC_EN0/1 pins to low to disable LVDS panel CABC function. This function will turn backlight automatically according to display content which may cause potential unstable backlight phenomena. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00221135: imx6x: clear PowerDown Enable bit of WDOG1_WMCRRobby Cai2012-08-24-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC spec: --- The Power down Counter inside WDOG-1 will be enabled out of reset. This counter has a fixed time-out value of 16 seconds, after which it will drive the WDOG-1 signal low. To prevent this, the software must disable this counter by clearing the PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR) within 16 seconds of reset de-assertion. Once disabled, this counter cannot be enabled again until the next system reset occurs. This feature is provided to prevent the hanging up of cores after reset, as WDOG-1 is not enabled out of reset. --- NOTE for the last sentence: This feature requires a dedicated WDOG_B pin for it. The fact that changing the IOMUX configuration can alter the WDOG_B functionality (GPIO by default) is not ideal as it defeats the purpose of this feature. But it still takes effect when the muxed pin is configured as WDOG_B within 16 seconds. Clear PDE bit to avoid WDOG_B (aka, WDOG-1) assertion. Tested on MX6SL. May add this for other MX6x. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00220824: mx6sl_evk: mmc: only SD1 supports 8bit on evk board.Ryan QIAN2012-08-21-4/+0
| | | | | | - configure SD1 to support 8bit on evk Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00217505-8 uboot: MX6Q-ARD: set the default gpmi clock to 20MHzHuang Shijie2012-08-20-3/+2
| | | | | | Set the default clock to 20MHz. The 11Mhz is too slow. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00220486 Modify ODT values for Solo AIAlejandro Sierra2012-08-20-4/+4
| | | | | | | | | | | | | | | | | | Modify ODT values for Solo AI. Some Solo boards did not passed the "mtest" from uboot using the previous configuration. Old configuration: MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) New configuration: MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) Signed-off-by: Alejandro Sierra <b18039@freescale.com>
* ENGR00220161: imx6sl: Add MX6SL EVK SupportRobby Cai2012-08-14-0/+2074
| | | | | | | | | Add mx6sl evk board support - copied from ARM2 board support - added a new board revision - removed unused boot device detection Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00220164 pfuze:rise VDDARM_IN to 1.425V and work around pfuze1.0Robin Gong2012-08-13-0/+45
| | | | | | | | | 1.Considering pfuze tolerance and IR drop and board ripple, need rise from 1.375V to 1.425V. Only for Sabresd. 2.workaround pfuze1.0 ER1, set all buck regulator except SW1C to PWM mode. now for mx6sl_arm2 and mx6_sabresd. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00219854-1 Enable fastboot feature on mx6q-arm2 boardLiGang2012-08-09-0/+47
| | | | | | | | 1. enable fastboot feature on mx6q-arm2 board 2. enlarge fastboot buffer to 320MB 3. correct some usb descriptors Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00218915-2 MX6 SabreSD:Use new 8bit bmp boot logoLiu Ying2012-08-03-5/+5
| | | | | | | | This patch changes to use new 8bit 600x400 bmp boot logo. As this boot logo has black background and white words, the user experience will be better. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218915-1 FSL common:Add new boot logoLiu Ying2012-08-03-1/+30159
| | | | | | | This patch adds new boot 8bit 600x400 bmp logo who has black background and white words. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218972 MX6 Secure Boot, Change to dynamic HAB data authenticationEric Sun2012-08-01-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original secure boot implementation make a consumption that u-boot.bin will not exceed 0x2F000. With this consumption, the hab data is hard coded in linker script file to relative address 0x2F000 without causing any problem. But when this consumption don't hold, the hard coded way will cause memory region overlap and break build. So we need to change to a dynamic way of allocating hab_data. The new implementation put hab data at the next 0x1000 alignment after u-boot data and text section, instead of hard coded to 0x2F000. Similar changes is made to uImage authentication implementation. Changes in U-Boot includes: - in u-boot.lds file, change "__hab_data" to dynamic align to 0x1000 - change authenticate_image implementation, originally the uImage parameters are hard coded, now they are retrived from the "load_addr" and the image_hdr The new secure image layout: U-Boot +-------------------+ DDR_START | | | U-Boot Image | | | +-------------------+ DDR_START + UBOOT_SIZE | PADDING | +-------------------+ align to 0x1000 | CSF Data | - +-------------------+ +-- CSF + Pad, Size : 0x2000 | PADDING | - +-------------------+ uImage +-------------------+ DDR_START | | | uImage | | | +-------------------+ DDR_START + UIMAGE_SIZE | PADDING | +-------------------+ align to 0x1000 | IVT | ---- Size : 0x20 +-------------------+ | CSF Data | - +-------------------+ +-- CSF + Pad, Size : 0x2000 | PADDING | - +-------------------+ Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00218583-1 MX6Q/DL SabreSD:Support LVDS1 splashimageLiu Ying2012-07-31-0/+9
| | | | | | | This patch configures iomux gpr3 register to enable LVDS1 via IPU1 DI1 if user chooses to use it. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218805 imx6: print the silicon revision correctlyJason Liu2012-07-30-11/+4
| | | | | | | | | | | | | | The silicon revision is not printed correctly, on ARM2 and sabrelite board, the log is just as the following: CPU: Freescale i.MX6 family TO0.0 at 792 MHz We need print the silicon revision correctly as: CPU: Freescale i.MX6 family TO1.2 at 792 MHz with i.mx6q TO1.2 chip Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00217401 common: fix build warningXinyu Chen2012-07-26-3/+1
| | | | | | | | | Fix the build warning in uboot build. Fix bug of incorrect dereference to periph2 clock pre divider. Fix incorrect type of maxpackage size assign, even it's not used at all in fastboot. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00218282 MX6Q: fix linker error when more configure enabled.Zhang Jiejing2012-07-25-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fix the linker error when enable more function(like CONFIG_NAND, CONFIG_SPASHSCREEN,etc) in uboot ARM2 board, and a possable linker error for other MX6 boards: /home/lambert/share/SATA2/R13.3/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/ bin/arm-eabi-ld: section .bss [27831000 -> 278666e7] overlaps section .rodata [2782387c -> 278609eb] /home/lambert/share/SATA2/R13.3/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/ bin/arm-eabi-ld: section .rodata.str1.1 [278609ec -> 27867803] overlaps section .bss [27831000 -> 278666e7] One issue here is: A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. Another issue is: The secure boot feature require __hab_data section in uboot linker script, but it's have a hard coding magic number, but if we enable more code, cause .text section bigger, it will cross the line, so it report the first linker error. This commit disable SECURE_BOOT feature by default for android, and comments if user want to use this feature, it needs change the .lds by there configure. Also, enlarge the magic number that this feature needs to cover if more code is build in. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00217764 MX6 Secure Boot : Fix NAND BOOT Failure due to secure patchEric Sun2012-07-23-7/+8
| | | | | | | | | | | | | | | | | | With the secure boot patch. MX6 NAND Boot is not functional. The root cause is that, the original secure boot patch fills "0xFF' to spacing regions, due to a issue in ROM code, read pages of all "0xff" will be treated as a critical error. Thus prevent the U-Boot from booting normally. The fix adjust image copy size in IVT so that when secure boot is not enabled, no unuseful data is copied by ROM code. Also the secure boot option is default disabled. The end user won't enable it unless they know what they are doing. These prevent the ROM code from copied pages of "0xff" data, and fix the issue. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00217381-01: mx6sl add sd1 and sd2 to support SD3.0Ryan QIAN2012-07-19-2/+2
| | | | | | enable SD3.0 support on SD1 and SD2 on mx6sl arm2 cpu board. Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00217114-1 MX6 U-Boot, Secure Boot, one code base for MX6Q/DL/SLEric Sun2012-07-13-171/+25
| | | | | | | | Move the secure boot related implementation code from mx6q_arm2.c to mx6/generic.c. In this way the HAB feature can be shared by all MX6 platforms Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00216852 MX6SL ARM2, UBoot : Apply V0.93 LPDDR2 ScriptEric Sun2012-07-13-17/+20
| | | | | | | | IC Validation team release new LPDDR2 script V0.93 in the following link, "http://compass.freescale.net/livelink/livelink?func=ll&objId=226733834/" Make changes to align to it Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00215197 pfuze MX6SL_ARM2: enable LDO bypass on u-bootimx-android-r13.5-alphaRobin Gong2012-07-04-0/+316
| | | | | | 1.enable I2C and I2C bus recovery support on mx6sl_arm2 2.enable LDO bypass on u-boot, by configuring 'CONFIG_MX6_INTER_LDO_BYPASS' Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00215633 MX6DL LPDDR2 : enable plugin mode of system bootEric Sun2012-07-03-1/+581
| | | | | | | | | | | | | | | | | | | | | For MX6DL LPDDR2 board, in order to use both the 2 channels of the memory, the "PL301_FAST2" must be set to 0x1. However this bit is not accessible using DCD. Plugin mode must be utilized for this purpose. The patch can be verified this way: Enter U-boot console > mw.l 0x80000000 0xC0 10 > mw.l 0x10000000 0xC1 10 > md.l 0x10000000 10 > md.l 0x80000000 10 Before the patch, 0x10000000 and 0x80000000 in fact point to the same memory location. So the last 2 dump will show memory content of both 0x000000C1 After the patch, 0x80000000 ponit to channel 0, 0x10000000 point to channel 1. the last 2 dump will show memory content of 0x000000C0 and 0x000000C1 respectively Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00215515 MX6: Move IPU QoS and VDOA/IPU/VPU AXI Cache config to kernelWayne Zou2012-07-02-70/+18
| | | | | | | Move IPU QoS and VDOA/IPU/VPU AXI Cache config to linux kernel in order to reduce code duplicate Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00214866 MX6SL ARM2, UBoot : Apply V0.91 LPDDR2 ScriptEric Sun2012-06-26-463/+397
| | | | | | | | | | | Validation team released lateset LPDDR2 script V0.91, See "http://compass.freescale.net/livelink/livelin k?func=ll&objId=226435628&objAction=browse&viewType=1" This change is necessary for bus freq scaling Apply it for both DCD mode and plugin mode. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00212571 [MX6]Change DRAM ODT setting to save powerAnson Huang2012-06-06-17/+17
| | | | | | | | | | | | | | | | We can use weak ODT setting, it will save about 50% DDR power in runtime. Now we use 0x00007 MMDC0_MPODTCTRL MMDC1_MPODTCTRL, (Ohm) Setting DDR_ODT imx_ODT Max_overclocking 0x22227 120 060 615MHz 0x11117 120 120 604MHz 0x00007 120 000 576MHz 0x00000 000 000 556MHz Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00211117 - U-Boot: Add EPDC splash screen for MX 6DL/S platformsDanny Nold2012-05-30-0/+590
| | | | | | | | | - EPDC Splash support for MX6DL/S Sabre SD - EPDC Splash support for MX6DL/S ARM2 - Currently, splash screen consists of a simple black border around a white screen. Done this way to save in memory footprint. Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00210918-2 cleanup android support, build pass all boardsZhang Jiejing2012-05-29-394/+18
| | | | | | | | | | - move recovery.h to common inlcude place. - move supported_reco_envs to soc related, not board related, - user can change this via configure header, don't needs this in every board file. - pass build for all mx5/mx6 android configs. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00210918-1 android: add mx6sl android supportZhang Jiejing2012-05-29-1/+34
| | | | | | | | | | - add android build config for mx6sl_arm2 board. - add gpio support for mx6sl - add boot image support - add android recovery support - add fastboot support, but fastboot cannot transfer file. Signed-off-by Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00209899-1 mx6x: add generic gpio interface.Zhang Jiejing2012-05-21-38/+19
| | | | | | | | | | | | | | | | | | | | | | Add generic gpio interface in uboot. Seems more and more gpio operation invoke in uboot, without RAW register operation, we should use generic gpio interface. you should define the CONFIG_MXC_GPIO use generic gpio interface: gpio_request, gpio_direction_output, gpio_direction_input, gpio_set_value, gpio_get_value, etc. Test on MX6Q, MX6DL. Other MX6X should also define this config. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00180103 MX6 sabreauto: Adjust IPU AXI-id0/1 Qos valueWayne Zou2012-05-16-6/+6
| | | | | | | | | set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7, mx6q use AXI-id0 for IPU display channel, it should has highest priority(bypass), and AXI-id1 for other IPU channel, it has high priority. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00209059 android: refine fastboot and recovery support.imx-android-r13.3Zhang Jiejing2012-05-14-142/+9
| | | | | | | | | | 1. add check asrc register to enter recovery mode, rather then check the file. 2. fix the boot.img can not fastboot flash function. 3. consolidate and cleanup fastboot code. 4. clean up many build warnning message. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00182739 sabresd I2C:add i2c recovery function in board_lateinitRobin Gong2012-05-11-4/+286
| | | | | | | | | | This issue have been found in mx53_smd(ENGR00163704), and found in sabresd if accessing pfuze while system reboot or reset, I2C bus will be blocked even if reboot,then pfuze will be failed to be probed, all device driver which use pfuze regulator will be impacted. In u-boot, we can check the SDA line low or high, if low, generate SCL and STOP signal to tell I2C device release I2C bus. Please check ENGR00163704 Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00182017 mx6dl sabresd I2C: fix build error and support mx6dl_sabresdRobin Gong2012-05-07-1/+1
| | | | | | | | | | | | | | 1.fix build error : mx6q_sabresd.c: In function 'setup_i2c': mx6q_sabresd.c:382: error: expected ')' before ';' token mx6q_sabresd.c:393: error: expected ';' before '}' token mx6q_sabresd.c: In function 'setup_pmic_voltages': mx6q_sabresd.c:399: warning: unused variable 'val' make[1]: *** [mx6q_sabresd.o] Error 1 2.modify mx6dl_sabresd_config to support pfuze on mx6dl sabresd board Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00181348 pfuze sabresd: pfuze support in u-bootRobin Gong2012-05-04-0/+128
| | | | | | add pfuze and I2C support, support cpu internal LDO bypass which can be enabled by CONFIG_MX6_INTER_LDO_BYPASS Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00181337-4 i.mx6 : i.mx6sl: Fix FEC RX CRC ErrorEric Sun2012-05-03-1/+10
| | | | | | | | | | | Since FEC_RX_ER is not connected with PHY(LAN8720A), we need either configure FEC_RX_ER PAD to other mode than FEC_RX_ER, or configure FEC_RX_ER PAD to FEC_RX_ER but need pull it down, otherwise, FEC MAC will report CRC error always. We configure FEC_RX_ER PAD to GPIO mode here and remove the SW hack which ignore the CRC error in fec driver Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00181337-3 i.mx6: i.mx6sl: add initial support for i.mx6sl ARM2 boardEric Sun2012-05-03-0/+1776
| | | | | | | | | | | | | | | | | This patch is to add the initial support for i.mx6sl ARM2 board, the patch does: - implemention of LPDDR2 init script - Plug-in/DCD mode support to do DDR initialization - Debug UART(UART1) support - SPI-NOR(M25P32, 4MB) flash support - FEC support, PHY(LAN8720A, RMII mode) - SD/MMC card support, SD1/SD2/SD3 Signed-off-by: Danny Nold <dannynold@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com> Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00180955 mx6q sabresd snvs TKT104835: fix long press ONOFF failed in u-bootRobin Gong2012-04-26-0/+11
| | | | | | | | | | | Need set Power Supply Glitch to 0x41736166 and clear Power Supply Glitch Detect bit when POR or reboot or power on, otherwise system could not be power off anymore, it will power up auto agian. These steps may be move to ROM code or fix by soc team in the future(PDM ticket number:TKT104835), anyway,u-boot fix the issue firsly. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00180623 fastboot: add fastboot in MX6Q_SABERSD boardsZhang Jiejing2012-04-24-12/+24
| | | | | | | | add fastboot function back in MX6Q_SABERSD board. the MX6DL_SABERSD have usb init related issue which will keep RESET, but left as later developement. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00179762: i.MX6: print the SOC revision correctlyJason Liu2012-04-18-3/+10
| | | | | | | | | | For example: The soc rev on i.mx6dl rev 1.0 not print correctly: CPU: Freescale i.MX 6 family 0.0V at 792 MHz This patch help u-boot print out the SOC revision correctly: CPU: Freescale i.MX6 family TO1.0 at 792 MHz Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179013 : MX6Solo/Quad : SABREAUTO: Add Parallel NOR SupportPrabhu Sundararaj2012-04-13-4/+127
| | | | | | | | | | | | | -Added u-boot config CONFIG_CMD_WEIMNOR for MX6Solo/Quad SABREAUTO to support WEIM NOR. - CONFIG_FLASH_HEADER_OFFSET is 0x1000 for WEIM NOR. -SPI NOR and WEIM NOR has pin conflicts, either one can be enabled. - mx6q_sabreauto_config, mx6solo_sabreauto_config configured default for SPI NOR. -In order to enable the read/write commands and to boot from WEIM NOR, need to enable the CONFIG_CMD_WEIMNOR. This will disable SPI-NOR Signed-off-by: Prabhu Sundararaj <b36876@freescale.com>
* ENGR00179000 i.mx6q/dl: sabresd: Add the splash screen supportJason Liu2012-04-13-102/+17
| | | | | | | | | | | | | | | | | | | | This patch will add the splash screen support for the i.mx6q/dl splash screen support. In order to enable the splash screen, you need make sure the following env variable has been set correctly: splashimage=0x30000000 splashpos=m,m lvds_num=0 The splash screen is default OFF, to enable it, please add: on i.mx6dq sabresd platform: define CONFIG_SPLASH_SCREEN in include/configs/mx6q_sabresd.h or on i.mx6dl sabresd platform: define CONFIG_SPLASH_SCREEN in include/configs/mx6dl_sabresd.h Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179150 MX6Q_ARM2 HAB Boot : avoid uImage authentication on un-fused chipEric Sun2012-04-09-23/+81
| | | | | | | | | Before running authentication on uImage in DDR, u-boot first check if SEC_CONFIG[1] (OTP_CFG5[1]) is burned. If so, it means the chip is in secure configuration, the authentication continues; if not, the chip in not in secure configuration, just bypass the authentication Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176537 mx6qsabreauto: i2c3_sda route settingAdrian Alonso2012-04-05-2/+24
| | | | | | | | | | * In RevB boards a steer logic circuit enables the route path of I2C3_SDA signal and is controlled by EIM_A24__GPIO_5_4 pad. * Configure GPIO_5_4 as as output and enable steer logic circuit. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00139223-1 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 1)Eric Sun2012-04-01-2/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first stage of High Assurance Boot (HAB) is the authentication of U-boot. A CST tool is used to generate the CSF data, which include public key, certificate and instruction of authentication process. Then it is attached to the original u-boot.bin The IVT should be modified to contain a pointer to the CSF data. The original u-boot.bin is with size between 0x27000 to 0x28000. For convinence, we first extend the u-boot.bin to 0x2F000 (with fill 0xFF). Then concatenate it with the CSF data. The combined image is again extend to a fixed length (0x31000), which is used as the IVT size parameter. The new memory layout is as the following. U-Boot Image +-------------+ | Blank | |-------------| 0x400 | IVT |-----------------------+ |-------------| | | | | | | | | | | |Remaining UB | | CSF pointer | | | | | | | | | |-------------| | | | | | Fill Data | | | | | |-------------| 0x2F000 <-------------+ | | | CSF Data | | | |-------------| | | | Fill Data | | | +-------------+ 0x31000 HAB APIs are ROM implemented, the entry table is located in a fixed location in the ROM. We export them so that during the HAB we can have some information about the secure boot process. For convinience some wrapper API is implemented based on the HAB APIs. - get_hab_status : used to dump information of authentication result - authenticate_image : used by u-boot to authenticate uImage For security hardware to function, CAAM related clock (CG0[4~6]) must be open. They are default closed in the original U-boot. "hab_caam_clock_enable" and "hab_caam_clock_disable" are created to open and close these clock gates. The generation of CSF data is not in the scope of this patch. CST tool will be used for this purpose. The procedure will be introduced in another document. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176834-4 - [imx]:add macro define to include chip head fileFugang Duan2012-03-31-1/+3
| | | | | | | - Different chip will include different head file, so add macro define to limit the use range. Signed-off-by: Fugang Duan <B38611@freescale.com>
generated by cgit v1.1 at 2024-11-25 13:30:14 +0000