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* tqm85xx: Remove board_add_ram_info()Peter Tyser2009-07-22-30/+3
| | | | | | | | This is in preparation for adding one common 8xxx board_add_ram_info() function for all 8xxx boards Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Redundant Environment: protect full sector sizeWolfgang Denk2009-06-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several boards used different ways to specify the size of the protected area when enabling flash write protection for the sectors holding the environment variables: some used CONFIG_ENV_SIZE and CONFIG_ENV_SIZE_REDUND, some used CONFIG_ENV_SECT_SIZE, and some even a mix of both for the "normal" and the "redundant" areas. Normally, this makes no difference at all. However, things are different when you have to deal with boards that can come with different types of flash chips, which may have different sector sizes. Here we may have to chose CONFIG_ENV_SECT_SIZE such that it fits the biggest sector size, which may include several sectors on boards using the smaller sector flash types. In such a case, using CONFIG_ENV_SIZE or CONFIG_ENV_SIZE_REDUND to enable the protection may lead to the case that only the first of these sectors get protected, while the following ones aren't. This is no real problem, but it can be confusing for the user - especially on boards that use CONFIG_ENV_SECT_SIZE to protect the "normal" areas, while using CONFIG_ENV_SIZE_REDUND for the "redundant" area. To avoid such inconsistencies, I changed all sucn boards that I found to consistently use CONFIG_ENV_SECT_SIZE for protection. This should not cause any functional changes to the code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Paul Ruhland Cc: Pantelis Antoniou <panto@intracom.gr> Cc: Stefan Roese <sr@denx.de> Cc: Gary Jennejohn <garyj@denx.de> Cc: Dave Ellis <DGE@sixnetio.com> Acked-by: Stefan Roese <sr@denx.de>
* fsl_pci: Move prototypes into fsl_pci.h and remove explicit externsKumar Gala2009-04-04-6/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.hKumar Gala2009-04-04-1/+1
| | | | | | | Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add multi-chip NAND support for the TQM8548 modulesWolfgang Grandegger2009-03-23-1/+4
| | | | | | | | | This patches configures the NAND UPM-FSL driver with multi-chip support for the Micron MT29F8G08FAB NAND flash memory on the TQM8548 modules. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-20-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* TQM85xx: Fix a couple warnings in TQM8548 buildAndy Fleming2009-02-16-3/+5
| | | | | | | | | | | | The ecm variable in sdram.c was being declared for all 8548, but only used by specific 8548 boards, so we make that variable require those specific boards, too The nand code was using an index "i" into a table, and then re-using "i" to set addresses for each upm. However, then it relied on the old value of i still being there to enable things. Changed the second "i" to "j" Signed-off-by: Andy Fleming <afleming@freescale.com>
* MPC85xx: TQM8548: workaround for erratum DDR 19 and 20Wolfgang Grandegger2009-02-16-8/+108
| | | | | | | | | This patch adds the workaround for erratum DDR20 according to MPC8548 Device Errata document, Rev. 1: "CKE signal may not function correctly after assertion of HRESET". Furthermore, the bug DDR19 is fixed in processor version 2.1 and the work-around must be removed. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548: use cache for AG and BE variantsWolfgang Grandegger2009-02-16-2/+2
| | | | | | | | | | | | This patch makes accesses to the system memory cachable by removing the caching-inhibited and guarded flags from the relevant TLB entries for the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards are configured similarly. This results in a big averall performace improvement. TFTP downloads, NAND Flash accesses, kernel boots, etc. are much faster. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548_AG: add 1 GiB DDR2-SDRAM configurationWolfgang Grandegger2009-02-16-4/+26
| | | | | | | | This patch add support for the 1 GiB DDR2-SDRAM on the TQM8548_AG module. Signed-off-by: Jens Gehrlein <sew_s@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548: fix SDRAM timing for 533 MHzWolfgang Grandegger2009-02-16-6/+8
| | | | | | | | | | According to new TQM8548 timing specification: Refresh Recovery: 34 -> 53 clocks CKE pulse width: 1 -> 3 cycles Window for four activities: 13 -> 14 cycles Signed-off-by: Jens Gehrlein <sew_s@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548: add support for the TQM8548_BE moduleWolfgang Grandegger2009-02-16-2/+4
| | | | | | | | | The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN interface. With NAND support, the image is significantly larger and TEXT_BASE is adjusted accordingly. U-Boot can be built for this module with "$ make TQM8548_BE_config". Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM85xx: make standard PCI/PCI-X configurableWolfgang Grandegger2009-02-16-6/+6
| | | | | | | | | The TQM8548_AG module does not have the standard PCI/PCI-X interface connected but just the PCI Express interface . So far it was not possible to disable it without disabling the complete PCI interface (CONFIG_PCI) including PCI Express. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM85xx: fix flash protection for boot loaderWolfgang Grandegger2009-02-16-2/+1
| | | | | | | | | | | | | | | | | | | | As the reset vector is located at 0xfffffffc, all flash sectors from the beginning of the U-Boot binary to 0xffffffff must be protected. On the TQM8548-AG having small sectors at the end of the flash it happened that the last two sector were not protected and an "erase all" left an un-bootable system behind: Bank # 2: CFI conformant FLASH (32 x 16) Size: 32 MB in 270 Sectors AMD Standard command set, Manufacturer ID: 0xEC, Device ID: 0x257E Erase timeout: 8192 ms, write timeout: 1 ms FFFA0000 E RO FFFC0000 RO FFFE0000 RO FFFE4000 RO FFFE8000 RO FFFEC000 RO FFFF0000 RO FFFF4000 RO FFFF8000 E FFFFC000 The same bug seems to be in drivers/mtd/cfi_flash.c:flash_init() and many board BSPs as well. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-1/+1
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: Add PORDEVSR_PCI1 definePeter Tyser2008-12-04-1/+1
| | | | | | | | | Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-0/+1
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-11-02-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-38/+20
| | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-108/+108
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-5/+5
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Moved initialization of EEPRO100 Ethernet controller to board_eth_init()Ben Warren2008-09-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards: db64360 db64460 katmai taihu taishan yucca cpc45 cpu87 eXalion elppc debris kvme080 mpc8315erdb integratorap ixdp425 oxc pm826 pm828 pm854 pm856 ppmc7xx sc3 sc520_spunk sorcery tqm8272 tqm85xx utx8245 Removed initialization of the driver from net/eth.c Also, wrapped contents of pci_eth_init() by CONFIG_PCI. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Fix merge problemsStefan Roese2008-08-06-1/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Cleanup out-or-tree building for some boards (.depend)Wolfgang Denk2008-07-02-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style CleanupWolfgang Denk2008-06-28-9/+9
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-1/+1
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* 85xx/86xx: Move to dynamic mgmt of LAWsKumar Gala2008-06-11-8/+8
| | | | | | | | | | | With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* TQM85xx: Change memory map to support Flash memory > 128 MiBWolfgang Grandegger2008-06-11-4/+122
| | | | | | | | | | | | | | | | | Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000). If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb). Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: NAND support via local bus UPMBWolfgang Grandegger2008-06-11-5/+480
| | | | | | | | | | | | | | | | | | | This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. It is now based on the re-written FSL NAND UPM driver. A patch has been posted earlier today with the subject: "NAND FSL UPM: driver re-write using the hwcontrol callback" Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time. Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM8548: PCI express supportWolfgang Grandegger2008-06-11-35/+215
| | | | | | | | | This patch adds support for PCI express cards. The board support now uses common FSL PCI init code, for both, PCI and PCIe on all TQM85xx modules. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM8548: Basic support for the TQM8548 modulesWolfgang Grandegger2008-06-11-15/+248
| | | | | | | | | | | | This patch adds basic support for the TQM8548 module from TQ-Components (http://www.tqc.de/) including DDR2 SDRAM initialisation and support for eTSEC 3 and 4 Furthermore Flash buffer write has been enabled to speed up output to the Flash by approx. a factor of 10. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Support for Flat Device TreeWolfgang Grandegger2008-06-11-0/+24
| | | | | | | | This patch adds support for Linux kernels using the Flat Device Tree. It also re-defines the default environment settings for booting Linux with the FDT blob. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Support for Intel 82527 compatible CAN controllerWolfgang Grandegger2008-06-10-0/+62
| | | | | | | | This patch adds initialization of the UPMC RAM to support up to two Intel 82527 compatible CAN controller on the TQM85xx modules. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Bugfix in the SDRAM initialisationWolfgang Grandegger2008-06-10-1/+3
| | | | | | | The CS0_BNDS register is now set according to the detected memory size. Signed-off-by Martin Krause <martin.krause@tqs.de>
* TQM85xx: Fix chip select configuration for second FLASH bankWolfgang Grandegger2008-06-10-38/+46
| | | | | | | This patch fixes the re-calculation of the automatic chip select configuration for boards with two populated FLASH banks. Signed-off-by: Martin Krause <martin.krause@tqs.de>
* TQM85xx: Fix CPM port pin configurationWolfgang Grandegger2008-06-10-0/+6
| | | | | | | | | Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560 board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used as serial interface anyway. Worse, on some board variants configuring the pins for SCC1 leads to short circuits (for example on the TQM8541-BG). Signed-off-by: Martin Krause <martin.krause@tqs.de>
* TQM85xx: Various coding style fixesWolfgang Grandegger2008-06-10-245/+251
| | | | Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM: move TQM boards to board/tqcWolfgang Grandegger2008-06-10-0/+1036
Move all TQM board directories to the vendor specific directory "tqc" for modules from TQ-Components GmbH (http://www.tqc.de). Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
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