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* MPC85xx: remove support for TQM85xx boardsWolfgang Denk2012-10-05-626/+0
| | | | | | | | | | | | Due to grown code sizes the TQM85xx boards don't build any more with some older tool chains (like ELDK 4.2). As these boards have long reached EOL it seems a waste of effort trying to fix them. The vendor has agreed to drop support for them, too. So let's get rid of them. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> cc: Kim Phillips <kim.phillips@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
* Fix incorrect use of getenv() before relocationWolfgang Denk2011-05-12-8/+11
| | | | | | | | | | | | | | | | | | | A large number of boards incorrectly used getenv() in their board init code running before relocation. In some cases this caused U-Boot to hang when certain environment variables grew too long. Fix the code to use getenv_r(). Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: The LEOX team <team@leox.org> Cc: Michael Schwingen <michael@schwingen.org> Cc: Georg Schardt <schardt@team-ctech.de> Cc: Werner Pfister <Pfister_Werner@intercontrol.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Peter De Schrijver <p2@mind.be> Cc: John Zhan <zhanz@sinovee.com> Cc: Rishi Bhattacharya <rishi@ti.com> Cc: Peter Tyser <ptyser@xes-inc.com>
* powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-29/+12
| | | | | | | | Remove duplicated code in TQM 85xx boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: wd@denx.de
* powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configuredKumar Gala2011-01-14-3/+2
| | | | | | | Now that we have serdes support for all 85xx/86xx/Pxxx chips we can replace the is_fsl_pci_cfg() code with the is_serdes_configured(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Clean up printing of PCI boot infoPeter Tyser2010-11-14-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
* TQM85xx: Fix bug introduced by 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-11-12-1/+1
| | | | | | | | | | The size of the other bank needed to be added to the br0 setting; this got dropped in the LBC cleanup. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* tqm85xx: Update PCI codePeter Tyser2010-10-20-109/+42
| | | | | | | | Update to use the recent, common FSL PCI initialization code. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: sr@denx.de Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliasesKumar Gala2010-07-20-6/+1
| | | | | | | | | | | Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-18/+17
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-1/+1
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* ppc/85xx: Move to using fsl_setup_hose on TQM 85xxKumar Gala2010-01-05-4/+4
| | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2009-09-08-5/+3
| | | | | | | | | | | Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-7/+0
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-6/+2
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Redundant Environment: protect full sector sizeWolfgang Denk2009-06-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several boards used different ways to specify the size of the protected area when enabling flash write protection for the sectors holding the environment variables: some used CONFIG_ENV_SIZE and CONFIG_ENV_SIZE_REDUND, some used CONFIG_ENV_SECT_SIZE, and some even a mix of both for the "normal" and the "redundant" areas. Normally, this makes no difference at all. However, things are different when you have to deal with boards that can come with different types of flash chips, which may have different sector sizes. Here we may have to chose CONFIG_ENV_SECT_SIZE such that it fits the biggest sector size, which may include several sectors on boards using the smaller sector flash types. In such a case, using CONFIG_ENV_SIZE or CONFIG_ENV_SIZE_REDUND to enable the protection may lead to the case that only the first of these sectors get protected, while the following ones aren't. This is no real problem, but it can be confusing for the user - especially on boards that use CONFIG_ENV_SECT_SIZE to protect the "normal" areas, while using CONFIG_ENV_SIZE_REDUND for the "redundant" area. To avoid such inconsistencies, I changed all sucn boards that I found to consistently use CONFIG_ENV_SECT_SIZE for protection. This should not cause any functional changes to the code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Paul Ruhland Cc: Pantelis Antoniou <panto@intracom.gr> Cc: Stefan Roese <sr@denx.de> Cc: Gary Jennejohn <garyj@denx.de> Cc: Dave Ellis <DGE@sixnetio.com> Acked-by: Stefan Roese <sr@denx.de>
* fsl_pci: Move prototypes into fsl_pci.h and remove explicit externsKumar Gala2009-04-04-6/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.hKumar Gala2009-04-04-1/+1
| | | | | | | Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC85xx: TQM85xx: make standard PCI/PCI-X configurableWolfgang Grandegger2009-02-16-6/+6
| | | | | | | | | The TQM8548_AG module does not have the standard PCI/PCI-X interface connected but just the PCI Express interface . So far it was not possible to disable it without disabling the complete PCI interface (CONFIG_PCI) including PCI Express. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM85xx: fix flash protection for boot loaderWolfgang Grandegger2009-02-16-2/+1
| | | | | | | | | | | | | | | | | | | | As the reset vector is located at 0xfffffffc, all flash sectors from the beginning of the U-Boot binary to 0xffffffff must be protected. On the TQM8548-AG having small sectors at the end of the flash it happened that the last two sector were not protected and an "erase all" left an un-bootable system behind: Bank # 2: CFI conformant FLASH (32 x 16) Size: 32 MB in 270 Sectors AMD Standard command set, Manufacturer ID: 0xEC, Device ID: 0x257E Erase timeout: 8192 ms, write timeout: 1 ms FFFA0000 E RO FFFC0000 RO FFFE0000 RO FFFE4000 RO FFFE8000 RO FFFEC000 RO FFFF0000 RO FFFF4000 RO FFFF8000 E FFFFC000 The same bug seems to be in drivers/mtd/cfi_flash.c:flash_init() and many board BSPs as well. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-1/+1
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: Add PORDEVSR_PCI1 definePeter Tyser2008-12-04-1/+1
| | | | | | | | | Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-11-02-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-38/+20
| | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-46/+46
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-5/+5
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Moved initialization of EEPRO100 Ethernet controller to board_eth_init()Ben Warren2008-09-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards: db64360 db64460 katmai taihu taishan yucca cpc45 cpu87 eXalion elppc debris kvme080 mpc8315erdb integratorap ixdp425 oxc pm826 pm828 pm854 pm856 ppmc7xx sc3 sc520_spunk sorcery tqm8272 tqm85xx utx8245 Removed initialization of the driver from net/eth.c Also, wrapped contents of pci_eth_init() by CONFIG_PCI. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Fix merge problemsStefan Roese2008-08-06-1/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* TQM8548: PCI express supportWolfgang Grandegger2008-06-11-31/+174
| | | | | | | | | This patch adds support for PCI express cards. The board support now uses common FSL PCI init code, for both, PCI and PCIe on all TQM85xx modules. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM8548: Basic support for the TQM8548 modulesWolfgang Grandegger2008-06-11-13/+100
| | | | | | | | | | | | This patch adds basic support for the TQM8548 module from TQ-Components (http://www.tqc.de/) including DDR2 SDRAM initialisation and support for eTSEC 3 and 4 Furthermore Flash buffer write has been enabled to speed up output to the Flash by approx. a factor of 10. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Support for Flat Device TreeWolfgang Grandegger2008-06-11-0/+24
| | | | | | | | This patch adds support for Linux kernels using the Flat Device Tree. It also re-defines the default environment settings for booting Linux with the FDT blob. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Support for Intel 82527 compatible CAN controllerWolfgang Grandegger2008-06-10-0/+57
| | | | | | | | This patch adds initialization of the UPMC RAM to support up to two Intel 82527 compatible CAN controller on the TQM85xx modules. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Fix chip select configuration for second FLASH bankWolfgang Grandegger2008-06-10-38/+46
| | | | | | | This patch fixes the re-calculation of the automatic chip select configuration for boards with two populated FLASH banks. Signed-off-by: Martin Krause <martin.krause@tqs.de>
* TQM85xx: Fix CPM port pin configurationWolfgang Grandegger2008-06-10-0/+6
| | | | | | | | | Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560 board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used as serial interface anyway. Worse, on some board variants configuring the pins for SCC1 leads to short circuits (for example on the TQM8541-BG). Signed-off-by: Martin Krause <martin.krause@tqs.de>
* TQM85xx: Various coding style fixesWolfgang Grandegger2008-06-10-165/+165
| | | | Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM: move TQM boards to board/tqcWolfgang Grandegger2008-06-10-0/+419
Move all TQM board directories to the vendor specific directory "tqc" for modules from TQ-Components GmbH (http://www.tqc.de). Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
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