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* ARM: keystone2: use SPD info to configure K2HK and K2E DDR3Vitaly Andrianov2016-03-14-63/+34
| | | | | | | | | | | | | | This commit replaces hard-coded EMIF and PHY DDR3 configurations for predefined SODIMMs to a calculated configuration. The SODIMM parameters are read from SODIMM's SPD and used to calculated the configuration. The current commit supports calculation for DDR3 with 1600MHz and 1333MHz only. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* keystone2: ddr3: eliminate using global ddr3_size variableVitaly Andrianov2015-02-16-9/+2
| | | | | | | | | | | | KS2 ddr3 initialization uses ddr3_size global variable before u-boot relocation. Even if the variable is not being used after relocation, writing to it corrupts relocation table. This patch removes the global ddr3_size variable and uses local one instead. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Nishanth Menon <nm@ti.com>
* keystone2: ecc: add ddr3 error detection and correction supportVitaly Andrianov2014-10-23-0/+16
| | | | | | | | | | | | | | | | | | | | This patch adds the DDR3 ECC support to enable ECC in the DDR3 EMIF controller for Keystone II devices. By default, ECC will only be enabled if RMW is supported in the DDR EMIF controller. The entire DDR memory will be scrubbed to zero using an EDMA channel after ECC is enabled and before u-boot is re-located to DDR memory. An ecc_test environment variable is added for ECC testing. If ecc_test is set to 0, a detection of 2-bit error will reset the device, if ecc_test is set to 1, 2-bit error detection will not reset the device, user can still boot the kernel to check the ECC error handling in kernel. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone: ddr3: workaround for ddr3a/3b memory issueMurali Karicheri2014-09-17-0/+4
| | | | | | | | | | | | | This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone: ddr3: move K2HK DDR3 configuration to a common fileHao Zhang2014-07-25-285/+20
| | | | | | | | | | | It's convenient to hold configurations for DDR3 PHY and EMIF in separate common place. This patch moves K2HK DDR3 PHY and EMIF configuration data with different rates and memory size to a common ddr3_cfg.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: move K2HK board files to common KS2 board directoryHao Zhang2014-07-25-0/+349
This patch moves K2HK board directory to a common Keystone II board directory. The Board related common functions are moved to a common keystone board file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>