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* ARM: beagle_x15: prevent DCAN1 _wait_target_disable failure in kernelRoger Quadros2015-07-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | If board is booted with transitions happening on DCAN1 pins then the following warning is seen in the kernel at boot when the hwmod layer initializes. "omap_hwmod: dcan1: _wait_target_disable failed" This is because DCAN1 module's SWAKEUP mechanism is broken and it fails to correctly turn OFF if it sees a transition on the DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode while enabling/disabling DCAN1 module. The hwmod layer enables and disables all modules at boot and we have no opportunity to put the DCAN1 pins in safe mode at that point. DCAN1 is not used by u-boot so it doesn't matter to it if these pins are in safe mode. The kernel driver correctly configures the right mode when DCAN1 is active. Signed-off-by: Roger Quadros <rogerq@ti.com> [trini: s/PULLUP/PULL_UP/ based on DRA7xx EVM version of this patch] Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: BeagleBoard-X15: Enable VTT regulatorLokesh Vutla2015-06-19-0/+23
| | | | | | | | BeagleBoard-X15 uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: BeagleBoard-x15: Add mux dataLokesh Vutla2015-06-12-38/+313
| | | | | | | | | | Adding the mux data, manual and virtual mode settings for BeagleBoard-X15. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
* ARM: BeagleBoard-x15: Enable IO delay recalibration sequenceLokesh Vutla2015-06-12-3/+11
| | | | | | | Enable IO delay recalibration sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-12-10/+0
| | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL registerLokesh Vutla2015-06-12-2/+2
| | | | | | | | When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: BeagleBoard-X15: Enable HW levelingLokesh Vutla2015-06-12-8/+18
| | | | | | | | Updating EMIF registers to enable HW leveling on BeagleBoard-X15. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: DDR3: Add support for HW levelingLokesh Vutla2015-06-12-2/+13
| | | | | | | | DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: BeagleBoard-x15: Rev A2x5: Change UART3 muxLokesh Vutla2015-05-27-2/+2
| | | | | | | | | | | UART3 RX and TX pins are now moved to support uart download capability on the platform. Old pins are now GPIOs routed to expansion ports. All original boards should either have been returned for modifications or already modified for the required change and maintaining compatibility for older boards are no longer needed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* net: cosmetic: Name ethaddr variables consistentlyJoe Hershberger2015-04-18-2/+2
| | | | | | | | Use "_ethaddr" at the end of variables and drop CamelCase. Make constant values actually 'const'. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.cKishon Vijay Abraham I2015-04-16-10/+0
| | | | | | | | | | | | | | | | Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY) changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between the two dwc3 controllers present in dra7xx/am43xx and enabled these clocks in enable_basic_clocks() in hw_data.c. However these clocks continued to be enabled in board files/driver files for dwc3 host mode functionality causing compilation break with few configs. Fixed it here by making all the clocks enabled in enable_basic_clocks() and removing it from board files/driver files here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register valueLokesh Vutla2015-02-16-2/+4
| | | | | | | | | | | The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* omap: beagle_x15: add MAINTAINERSMasahiro Yamada2015-01-12-0/+6
| | | | | | | | Commit 1e4ad74b875f (beagle_x15: add board support for Beagle x15) missed to add board/ti/beagle_x15/MAINTAINERS. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Felipe Balbi <balbi@ti.com>
* beagle_x15: add board support for Beagle x15Felipe Balbi2014-12-04-0/+470
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet. For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
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