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* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-1/+1
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: socrates: fix DDR SDRAM tlb entry configurationAnatolij Gustschin2008-12-03-0/+2
| | | | | | | | | | | | | | | | | | | | | since commit be0bd8234b9777ecd63c4c686f72af070d886517 tlb entry for socrates DDR SDRAM will be reconfigured by setup_ddr_tlbs() from initdram() causing an inconsistency with previously configured DDR SDRAM tlb entry from tlb_table: socrates>l2cam 7 9 IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS 7 : 00 00000000 256MB V 0 -> 0_00000000 0000 -I-G- ---RWX 8 : 00 00000000 256MB V 0 -> 0_00000000 0000 ----- ---RWX 9 : 00 10000000 256MB V 0 -> 0_10000000 0000 ----- ---RWX This patch makes the presence of the DDR SDRAM tlb entry in the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this inconsistency. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Andy Fleming <afleming@freescale.com>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-0/+1
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-1/+4
| | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-96/+96
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* socrates: fix crash after relocationAnatolij Gustschin2008-09-22-1/+1
| | | | | | | | | | Currently U-Boot crashes after relocation to RAM. Changing the CPO value of the DDR SDRAM TIMING_CFG_2 register to READ_LAT + 1 (to the value it was before conversion of socrates to new DDR code) fixes the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 85xx: socrates: autoprobe Lime chipu-boot@bugs.denx.de2008-09-13-15/+43
| | | | | | | | | This patch is an attempt to implement autoprobing for the Lime presence on the bus. Configure GPCM for Lime CS2 and try to access chip ID registers. Second read atempt delivers register values if the chip is present. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-4/+4
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* 85xx: socrates: Enable Lime support.Anatolij Gustschin2008-09-09-2/+233
| | | | | | | | | This patch adds Lime GDC support together with support for the PWM backlight control through the w83782d chip. The reset pin of the latter is attached to GPIO, so we need to reset it in early_board_init_r. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 85xx: Socrates: Major code update.Detlev Zundel2008-09-09-49/+65
| | | | | | | | | | | | | | | | | - Update the local bus ranges in the FDT for Linux for the various devices connected to the local bus via chip-select. - Set the LCRR_DBYP bit in the LCRR for local bus frequencies lower than 66 MHz and uses I/O accessor functions consequently. - UPM data update. - Update of default environment and configuration. Use I2C multibus as we do have two I2C buses. Also enable sdram and ext2 commands. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Detlev Zundel <dzu@denx.de>
* FSL DDR: Convert socrates to new DDR code.Kumar Gala2008-08-27-5/+93
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* socrates: Update NAND driver to new API.Scott Wood2008-08-13-52/+32
| | | | | | | Also, fix some minor formatting issues, and simplify the handling of "state" for writes. Signed-off-by: Scott Wood <scottwood@freescale.com>
* Cleanup out-or-tree building for some boards (.depend)Wolfgang Denk2008-07-02-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style CleanupWolfgang Denk2008-06-28-16/+16
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-1/+1
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* 85xx/86xx: Move to dynamic mgmt of LAWsKumar Gala2008-06-11-5/+5
| | | | | | | | | | | With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* Socrates: Added FPGA base address update in FDT.Sergei Poselenov2008-06-11-0/+10
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Socrates: NAND support added. Changed the U-Boot base address andSergei Poselenov2008-06-11-3/+220
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Socrates: added missed file with UPMA configuration data.Sergei Poselenov2008-06-11-0/+55
| | | | Signed-of-by: Sergei Poselenov <sposelenov@emcraft.com>
* Socrates: Added FPGA mapping. LAWs and TLBs cleanup.Sergei Poselenov2008-06-11-25/+23
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* socrates: Fix PCI clk fix patchAndy Fleming2008-06-10-1/+3
| | | | | | | | | The submitted patch seems to have been more up-to-date, but an older patch was already in the repository. This patch encompasses the differences Taken entirely from Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Socrates: Fix PCI bus frequency reportSergei Poselenov2008-05-27-2/+11
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* socrates: changes to support FDTSergei Poselenov2008-05-20-0/+25
| | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Initial support for "Socrates" boardSergei Poselenov2008-05-20-0/+715
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
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