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* Tegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhuTom Warren2013-05-28-0/+38
| | | | | | | | | | Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both board and board_name == beaver. Didn't test as I have no T30 Beaver board here. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* Tegra: T30: Beaver board support.Tom Warren2013-04-15-0/+71
| | | | | | | | Beaver is a Tegra30 board that is nearly 100% compatible w/Cardhu. Add a Beaver build so it can begin to be differentiated, if need be. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: Split tegra_get_chip_type() into soc & sku funcsTom Warren2013-04-15-1/+1
| | | | | | | | | | | As suggested by Stephen Warren, use tegra_get_chip() to return the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true function, i.e. tegra_get_chip_sku(), which returns an ID like TEGRA_SOC_T25, TEGRA_SOC_T33, etc. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: MMC: Add SD bus power-rail init routineTom Warren2013-03-25-0/+62
| | | | | | | T114 requires SD bus power-rail bringup for the SDIO card on SDMMC3. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config tableTom Warren2013-03-25-0/+10
| | | | | | | | SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup before the MMC driver is added. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: fdt: Add SDMMC (sdhci) nodes for T114 boards (Dalmore for now)Tom Warren2013-03-25-0/+13
| | | | | | | Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra114: dalmore: fdt: enable dalmore SPI controllerAllen Martin2013-03-25-0/+5
| | | | | | | | | Dalmore has a SPI flash part attached to controller 4, so enable controller 4 and set to 25MHz. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* spi: add common fdt SPI driver interfaceAllen Martin2013-03-25-1/+1
| | | | | | | | | | | Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: spi: rename tegra SPI driversAllen Martin2013-03-25-1/+1
| | | | | | | | | Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: remove support for UART SPI switchAllen Martin2013-03-25-130/+1
| | | | | | | | | | This feature was only used for tegra20 seaboard that had a pinmux conflict on the SPI pins. These boards were never manufactured, so remove this support to clean up SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: Dalmore: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-0/+12
| | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: fdt: Move aliases from dtsi to dts file as per other TegrasTom Warren2013-03-14-0/+8
| | | | | | | All other Tegra boards have their alias nodes in the .dts file Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: Dalmore: Always use DEFAULT instead of DISABLE for lock bitsTom Warren2013-03-14-12/+12
| | | | | | | | | | | | | | The pinmux code issues a warning if the caller attempts to disable the lock bit in a pinmux register, since this is impossible (once it's locked, the only way to unlock it is to reset the device/pmt controller). The I2C/DDC/CEC/USB macros expect a lock setting to be passed in, and the previous setting of DISABLE caused the pinmux table parsing code to issue the warning. Changing the lock bits in these table entries to DEFAULT (i.e. don't touch it) fixes this. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routinesTom Warren2013-03-14-1/+81
| | | | | | | T30 requires specific SDMMC pad programming, and bus power-rail bringup. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)Tom Warren2013-03-14-0/+15
| | | | | | | Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: Cardhu: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-3/+24
| | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 initTom Warren2013-03-14-180/+286
| | | | | | | | | | | | | Use the latest tables & code from our internal U-Boot repo. The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup table were off by a few indices, causing the pinmux init code to write bad data to the PINMUX_AUX_ regs. This also enabled the lock bit, which made it impossible to reconfig the pads correctly for SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N, USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: Cardhu: Remove unneeded cardhu.c.mmc fileTom Warren2013-03-14-151/+0
| | | | | | | | This was an older debug/developmental file that got added accidentally. Not needed/used in any Cardhu build. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)Tom Warren2013-03-14-0/+5
| | | | | | | Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: fdt: Remove memreserve line from Cardhu/Seaboard DT filesTom Warren2013-03-14-2/+0
| | | | | | | Not used, and wrong in Cardhu's case Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: MMC: Add DT support to MMC driver for all T20 boardsTom Warren2013-03-14-74/+32
| | | | | | | | | | | | tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT filesTom Warren2013-03-14-6/+56
| | | | | | | | | | Linux dts files were used for those boards that didn't already have sdhci info populated. Tamonten has their own dtsi file with common sdhci nodes (sourced from Linux). Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: fdt: Change /include/ to #include for C preprocessorTom Warren2013-03-14-6/+6
| | | | | | | | | dts Makefile has the arch & board include paths added to DTS_CPPFLAGS. This allows the use of '#include "xyz"' in the dts/dtsi file which helps the C preprocessor find common dtsi include files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: fdt: Update DT files with I2C info for T114/DalmoreTom Warren2013-03-14-0/+25
| | | | | | | | | | | T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: usb: move implementation into right directoryLucas Stach2013-03-14-1/+1
| | | | | | | | | | | | | | | | This moves the Tegra USB implementation into the drivers/usb/host directory. Note that this merges the old /arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code changes, just moving stuff around. v2: While at it also move some defines and the usb.h header file to make usb driver usable for Tegra30. NOTE: A lot more work is required to properly init the PHYs and PLL_U on Tegra30, this is just to make porting easier and it does no harm here. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra114: Add/enable Dalmore build (T114 reference board)Tom Warren2013-02-11-0/+317
| | | | | | | This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD. Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra114: Add generic Tegra114 build supportTom Warren2013-02-11-1/+1
| | | | | | | This patch adds basic Tegra114 (T114) build support - no specific board is targeted. Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra114: Dalmore: Add DT filesTom Warren2013-02-11-0/+13
| | | | | | | | These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add SPI SLINK driverAllen Martin2013-02-11-1/+2
| | | | | | | | | | | | | | | | | | | | | | Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra30: fdt: add SPI SLINK nodesAllen Martin2013-02-11-0/+5
| | | | | | | | Add tegra30 SPI SLINK nodes to fdt. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: add back missing host1x nodeAllen Martin2013-02-11-0/+11
| | | | | | | | Add back host1x node to seaboard dts file. This got dropped during the tegra fdt sort. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: sort dts filesAllen Martin2013-01-17-70/+58
| | | | | | | | | | | | | | Sort nodes in dts files according the the following rules: 1) Any nodes that already exist in any /include/d file, in the order they appear in the /include/d file. 2) Any nodes with a reg property, in order of their address. 3) Any nodes without a reg property, alphabetically by node name. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: remove clocks nodesAllen Martin2013-01-17-59/+0
| | | | | | | These nodes are unused. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: remove IRDA pinmux synonymAllen Martin2013-01-16-2/+2
| | | | | | | | | IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this synonym and replace with UARTB to disambiguate. Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra30: fdt: Update DT files with I2C info for T30/CardhuTom Warren2013-01-16-0/+41
| | | | | | | | | | | Note that T30 does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but DVC_I2C is still used to designate the controller intended for power control (PWR_I2C in the schematics). On Cardhu, it's used to access the PMU and EEPROM, as well as the audio codec, temp sensor, and fuel gauge devices from the OS. Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra30: Add/enable Cardhu build (T30 reference board)Tom Warren2013-01-16-0/+563
| | | | | | | | | | | This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD. include/configs/tegra-common.h now holds common config options for Tegra SoCs. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: Add generic Tegra30 build supportTom Warren2013-01-16-3/+14
| | | | | | | | This patch adds basic Tegra30 (T30) build support - no specific board is targeted. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: Cardhu: Add DT filesTom Warren2013-01-16-0/+14
| | | | | | | | | These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: display: add board pinmuxMarc Dietrich2013-01-16-0/+7
| | | | | | | | Boards may require a different pinmux setup for DISPALY than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: enable 8-bit SD slots in board filesStephen Warren2012-11-19-6/+4
| | | | | | | | | | | | | | | | | | | | Harmony contains an SD slot with all 8 bits routed. This allows plugging in an eMMC-chip-in-SD-form-factor. Seaboard/Springbank/Ventana/AC100 all have an eMMC chip with all 8 bits hooked up. Now that the U-Boot eMMC code fully supports 8-bit operation, initialize those ports as 8-bit instead of 4-bit to improve performance. Whistler was already registering its ports as 8-bit. TrimSlice doesn't have any 8-bit ports. I don't have any Avionic Design boards nor the Colibri board to test with. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add LCD definitions for SeaboardSimon Glass2012-11-19-0/+33
| | | | | | | | The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled by one of the PWMs. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add LCD support to Nvidia boardsSimon Glass2012-11-19-0/+19
| | | | | | | Add calls to the LCD driver from Nvidia board code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add support for PWMSimon Glass2012-11-19-0/+5
| | | | | | | | The pulse width/frequency modulation peripheral supports generating a repeating pulse. It is useful for controlling LCD brightness. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: don't request GPIO from Seaboard's SPLStephen Warren2012-10-29-10/+4
| | | | | | | | | | | | | | | | Seaboard has a GPIO that switches an external mux between Tegra's debug UART and SPI flash. This is initialized from the SPL so that SPL debug output can be seen. Simplify the code that does this, and don't actually request the GPIO in the SPL; just program it. This saves ~4.5K from the size of the SPL, mostly BSS due to the large gpio_names[] table that is no longer required. This makes Seaboard's SPL fit within the current max size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: select between Seaboard/Ventana at compile timeStephen Warren2012-10-29-3/+1
| | | | | | | | | | | | | | Seaboard and Ventana are very similar boards, and so share the seaboard.c board file. The one difference needed so far is detected at run-time by calling machine_is_ventana(). This bloats the Ventana build with code that is never used. Switch to detecting Ventana at compile time to remove bloat. This shaves ~5K off the SPL size on Ventana, and makes the SPL fit within the max size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Whistler: remove unused USB aliasStephen Warren2012-10-29-1/+4
| | | | | | | | | | | Port USB1 on Whistler is intended as a device port for USB recovery. Whistler's DT currently contains an alias for this USB port, even though Whistler's config doesn't enable multiple USB controllers, so the alias is unused. Remove the unused alias for consistency for now. Similar, explicitly disable the port in the device tree too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Harmony: enable ULPI USB portStephen Warren2012-10-29-1/+11
| | | | | | | | | | | | The ULPI port is routed onto pins on the mini PCI Express connector. A standard breakout board may be used to access the port. * Add required DT entries to configure the ULPI port. * Setup up the ULPI pinmux in the board code. * Enable multiple USB controller and ULPI support in the board config. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: move common features to a common makefileMarc Dietrich2012-10-29-3/+5
| | | | | | | | | | | | | | | | | | | For Non-Nvidia boards to include newly added features (like emc clock scaling) it would be necessary to add each feature to their own board Makefile. This is because currently the top Makefile automaticly includes these features only for Nvidia boards. This patch adds a simple Makefile include so all new features become available for non-Nvidia board vendors. Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Thierry Reding <thierry.reding@avionic-design.de> Cc: Lucas Stach <dev@lynxeye.de> Signed-off-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: add board pinmuxLucas Stach2012-10-15-0/+12
| | | | | | | | Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: clean up board include hellLucas Stach2012-10-15-39/+1
| | | | | | | | | | The prototypes used in board files were all scattered out, which lead to code duplication between SPL and normal U-Boot and some prototypes not actually being used. Consolidate this in a common board header. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-12-19 02:01:28 +0000