summaryrefslogtreecommitdiff
path: root/board/mpc8360emds
Commit message (Collapse)AuthorAgeLines
* Clenaup, update CHANGELOGWolfgang Denk2007-04-18-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Moved fdt command support code to fdt_support.cGerald Van Baren2007-04-06-3/+13
| | | | | ...in preparation for improving the bootm command's handling of fdt blobs. Also cleaned up some coding sloppiness.
* Minor cleanup.Wolfgang Denk2007-04-04-1/+0
|
* Add a flattened device tree (fdt) command (2 of 2)Gerald Van Baren2007-03-31-6/+50
| | | | Modifications to the existing code to support the new fdt command.
* mpc83xx: fix implicit declaration of function 'ft_get_prop' warningsKim Phillips2007-03-02-0/+3
| | | | (cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)
* mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffersKim Phillips2007-03-02-1/+8
| | | | | | | | | | Disable G1TXCLK, G2TXCLK h/w buffers. This patch fixes a networking timeout issue with MPC8360EA (Rev.2) PBs. Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Emilian Medve <Emilian.Medve@freescale.com>
* mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xxXie Xiaobo2007-03-02-0/+15
| | | | | | | The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. it pass DDR/DDR2 compliance tests. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
* mpc83xx: Update 83xx to use fsl_i2c.cTimur Tabi2006-11-03-10/+3
| | | | | | | | Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-9/+9
| | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Fix the incorrect dcbz operationDave Liu2006-11-03-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 834x rev1.x silicon has one CPU5 errata. The issue is when the data cache locked with HID0[DLOCK], the dcbz instruction looks like no-op inst. The right behavior of the data cache is when the data cache Locked with HID0[DLOCK], the dcbz instruction allocates new tags in cache. The 834x rev3.0 and later and 8360 have not this bug inside. So, when 834x rev3.0/8360 are working with ECC, the dcbz instruction will corrupt the stack in cache, the processor will checkstop reset. However, the 834x rev1.x can work with ECC with these code, because the sillicon has this cache bug. The dcbz will not corrupt the stack in cache. Really, it is the fault code running on fault sillicon. This patch fix the incorrect dcbz operation. Instead of CPU FP writing to initialise the ECC. CHANGELOG: * Fix the incorrect dcbz operation instead of CPU FP writing to initialise the ECC memory. Otherwise, it will corrupt the stack in cache, The processor will checkstop reset. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: add OF_FLAT_TREE bits to 83xx boardsKim Phillips2006-11-03-0/+42
| | | | | | | | | | add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and STDOUT_PATH configuration bits to mpc8349emds, mpc8349itx, and mpc8360emds board code. redo environment to use bootm with the fdtaddr for booting ARCH=powerpc kernels by default, and provide default fdtaddr values.
* mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and ↵Timur Tabi2006-11-03-2/+9
| | | | | | | | | MPC8360EMDS This patch also adds an improved I2C set_speed(), which handles all clock frequencies. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: add QE ethernet supportDave Liu2006-11-03-0/+56
| | | | this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
* mpc83xx: Add MPC8360EMDS basic board supportDave Liu2006-11-03-0/+1069
Add support for the Freescale MPC8360EMDS board. Includes DDR, DUART, Local Bus, PCI.
generated by cgit v1.1 at 2024-12-28 05:33:43 +0000