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path: root/board/google/chromebook_link/link.c
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* x86: Drop all the old pin configuration codeSimon Glass2016-03-17-138/+0
| | | | | | | | We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move northbridge and PCH init into driversSimon Glass2016-01-24-8/+0
| | | | | | | | | | Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: cros_ec: Drop unnecessary initSimon Glass2015-04-18-3/+0
| | | | | | | Since driver model will probe the EC when it is first used, we do not need to init it explicitly. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: pci: Convert coreboot to use driver model for pciSimon Glass2015-04-18-0/+9
| | | | | | Move coreboot-x86 over to driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-1/+1
| | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-0/+40
| | | | | | | | | Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: chromebook_link: Enable the Chrome OS ECSimon Glass2014-11-25-0/+4
| | | | | | Enable the Chrome OS EC so that it can be used from U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove board_early_init_r()Simon Glass2014-11-25-5/+0
| | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: chromebook_link: Enable GPIO supportSimon Glass2014-11-21-0/+107
| | | | | | | Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add chromebook_link boardSimon Glass2014-11-21-0/+17
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
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