arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	x86: ivybridge: Do not require HAVE_INTEL_ME	Bin Meng	2016-01-13	-0/+1
\| \| \| \| \| \| \| \| \|	Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
*	x86: Remove HAVE_ACPI_RESUME	Bin Meng	2015-12-09	-1/+0
\| \| \| \| \| \| \| \| \|	These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
*	x86: Remove CPU_INTEL_SOCKET_RPGA989	Bin Meng	2015-12-09	-1/+0
\| \| \| \| \| \| \| \| \| \|	This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
*	x86: Clean up ivybridge/chrome Kconfig options	Bin Meng	2015-12-09	-1/+0
\| \| \| \| \| \| \| \| \| \|	There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
*	x86: Remove MARK_GRAPHICS_MEM_WRCOMB	Bin Meng	2015-07-14	-1/+0
\| \| \| \| \| \| \| \|	MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
*	x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONS	Bin Meng	2015-04-29	-0/+3
\| \| \| \| \| \| \| \| \|	Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define the text base address. Since it is deprecated, just remove it and use CONFIG_SYS_TEXT_BASE directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
*	x86: Rename MMCONF_BASE_ADDRESS and make it common across x86	Simon Glass	2015-02-05	-2/+1
\| \| \| \| \| \| \| \| \|	This setting will be used by more than just ivybridge so make it common. Also rename it to PCIE_ECAM_BASE which is a more descriptive name. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
*	x86: Move CONFIG_SYS_CAR_xxx to Kconfig	Bin Meng	2015-01-13	-0/+8
\| \| \| \| \| \| \| \| \| \|	Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that we don't need them in the board configuration file thus the same board configuratoin file can be used to build both coreboot version and bare version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
*	x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig	Bin Meng	2015-01-13	-0/+1
\| \| \| \| \| \| \| \|	Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig options so that we can remove them from board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
*	x86: Make ROM_SIZE configurable in Kconfig	Bin Meng	2014-12-13	-0/+1
\| \| \| \| \| \| \| \| \| \|	Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
*	x86: chromebook_link: Implement CAR support (cache as RAM)	Simon Glass	2014-11-21	-0/+12
\| \| \| \| \| \| \| \|	Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: Emit post codes in startup code for Chromebooks	Simon Glass	2014-11-21	-0/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
*	x86: Add chromebook_link board	Simon Glass	2014-11-21	-0/+15
	This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>