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* arm: ls102xa: Add snoop disable for slave port 0, 1 and 2Jason Jin2014-11-24-0/+17
| | | | | | | | | Disable the snoop for slave interface 0, 1 and 2 to avoid the interleaving on the CCI400 BUS. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* qe: add qe support for ls1021a-twr boardZhao Qiang2014-11-19-0/+8
| | | | | Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* qe: add qe support to ls1021aqdsZhao Qiang2014-11-19-0/+8
| | | | | | | add qe support to ls1021aqds Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-11-14-0/+239
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| * powerpc/BSC9131RDB: Enable creation of dynamic partitions for NANDAshish Kumar2014-11-14-0/+11
| | | | | | | | | | | | | | | | | | | | * fdt_fixup_mtdparts is called from ft_board_setup * Run "mtdparts default" to create NAND partition on uboot * Use mtdparts to create partitions dynamically rather than using static partitions in device tree Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/BSC9132QDS: Enable creation of dynamic partition for NAND and NORAshish Kumar2014-11-14-0/+12
| | | | | | | | | | | | | | | | | | | | * fdt_fixup_mtdparts is called from ft_board_setup * run "mtdparts default" to create NAND, NOR partition on uboot * Use mtdparts to create partitions dynamically rather than using static partitions in device tree Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfgPriyanka Jain2014-11-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -A_007662 states that for x1 link width, PCIe2 controller trains in Gen1 speed while configured for Gen2 speed. Workaround:Set the width to x1 and speed to Gen2 by writing to CCSR registers in PBI phase -A_008007 states that PVR register may show random value. Workaround: Reset PVR register using DCSR space in PBI phase Add PBI based software workaround for A_007662 and A_008007 in t104x_pbi.cfg. This is required for SPL-based bootloaders like NAND-boot, SD-boot, SPI-boot Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t4rdb: Add support of CPLDChunhe Lan2014-11-14-0/+206
| | | | | | | | | | | | | | | | | | | | | | This support of CPLD includes - Files and register definitions - Command to switch alternate bank - Command to switch default bank Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mx6sabresd: Staticize when possibleFabio Estevam2014-11-13-6/+6
| | | | | | | | | | | | Annotate 'static' when appropriate for the variables used locally. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx6sabresd: Fix error handling in board_mmc_init()Fabio Estevam2014-11-13-4/+6
| | | | | | | | | | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx6: SPL support for iMX6 SabreSDJohn Tobias2014-11-13-2/+184
| | | | | | | | | | | | | | | | This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port (Switch 1 or 2 of SW6) Signed-off-by: John Tobias <john.tobias.ph@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | imx6: add data configuration file for SPLJohn Tobias2014-11-13-0/+58
| | | | | | | | | | | | | | It's a trim version of mx6q_4x_mt41j128.cfg. It just removed the related settings for DDR Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
* | imx: mx6q/dlsabreauto: And NAND flash supportYe.Li2014-11-13-0/+66
| | | | | | | | | | | | | | | | | | | | | | The i.MX6Q/DL sabreauto board has one NAND socket, set the CONFIG_NAND_MXS and relevant NAND configurations to enable the MXS NAND flash driver. Add board level codes to set IOMUX and clock for GPMI-NAND and BCH module. Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx53loco: Change 'fdt_file' dynamicallyFabio Estevam2014-11-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Since kernel 3.15 there are two dtb's for the imx53-qsb board: imx53-qsb.dtb - For the boards with DA9053 PMIC imx53-qsrb.dtb - For the boards with MC34708 PMIC Change the 'fdt_file' dynamically, so that the correct dtb can be used depending on the board variant. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* | mx28evk: README: Revision C is also supportedFabio Estevam2014-11-12-1/+1
|/ | | | | | Adjust the text to mention that rev C of the board is also supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-05-6/+253
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| * imx: mx6 sabreauto: Add board support for USB EHCIYe.Li2014-11-03-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx6 sabreauto board, there are two USB ports: 0: OTG 1: HOST The EHCI driver is enabled for this board, but the IOMUX and VBUS power control is not implemented, which cause both USB port failed to work. This patch fix the problem by adding the board support codes. Since the power control uses the GPIO pin from port expander MAX7310, the PCA953X driver is enabled for accessing the MAX7310. The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting its daisy chain. Add a new function "imx_iomux_set_gpr_register" to handle GPR register setting. Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6slevk: Add support for USDHC1 and USDHC3 slotsYe.Li2014-11-03-6/+99
| | | | | | | | | | | | | | | | | | There are three SD/MMC sockets on mx6slevk boards. Implements the full support for them. The default boot socket is USDHC2, so the MMC environment is set to that device. Signed-off-by: Ye.Li <B37916@freescale.com>
| * mx6sabresd: Add Seiko WVGA panel supportFabio Estevam2014-10-30-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the 4.3'' Seiko WVGA parallel display. In order to direct the splash screen to the Seiko display: => setenv panel SEIKO-WVGA => save => reset Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | kconfig: arm: introduce symbol for ARM CPUsGeorges Savoundararadj2014-10-29-57/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a Kconfig symbol for each ARM CPU: CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136, CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100. Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected for CPU_ARM1176 and CPU_V7. For each target, the corresponding CPU is selected and the definition of SYS_CPU in the corresponding Kconfig file is removed. Also, it removes redundant "string" type in some Kconfig files. Signed-off-by: Georges Savoundararadj <savoundg@gmail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxTom Rini2014-10-27-2/+2
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| * | powerpc: mpc5121ads: update board config info in READMEAnatolij Gustschin2014-10-27-2/+2
| | | | | | | | | | | | | | | | | | | | | The config targets described in README are not present any more, update the info to currently used targets. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2014-10-27-1/+61
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| * mx6qsabreauto: Add HDMI supportFabio Estevam2014-10-21-1/+59
| | | | | | | | | | | | Let HDMI splash screen support work by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ARM: i.MX: provide declaration for board_spi_cs_gpioEric Nelson2014-10-21-0/+2
| | | | | | | | | | | | | | | | Provide a public declaration of the board_spi_cs_gpio() callback for i.MX SPI chip selects to prevent the warning "Should it be static?" when compiling with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | ls102x: Add support for secure boot and enable blob commandRuchika Gupta2014-10-16-0/+2
| | | | | | | | | | Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ls102x: configs - Add hash command in freescale LS1 platformsRuchika Gupta2014-10-16-0/+20
|/ | | | | | | | | Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2014-10-08-19/+713
|\ | | | | | | | | | | | | The single file conflict below is actually trivial. Conflicts: board/boundary/nitrogen6x/nitrogen6x.c
| * imx: mx6dlarm2: Add support for i.MX6Q/DL arm2 LPDDR2 boardsYe.Li2014-09-30-7/+510
| | | | | | | | | | | | | | | | Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2 arm2 board. Since the LPDDR2 arm2 board has different DDR size, use CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE. Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6dlarm2: Add support for i.MX6DL arm2 DDR3 boardYe.Li2014-09-30-0/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2 shared the same board with i.MX6Q ARM2 board since the i.MX6DL is pin-pin compatible with i.MX6Q. The patch also support the DDR 32-BIT mode option. Please define CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT mode.But due to the board design, it's 64bit DDR buswidth physically, so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it. Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: ddr: Move mx6q_4x_mt41j128.cfg to mx6sabresd boardNitin Garg2014-09-22-0/+0
| | | | | | | | | | | | | | | | | | | | Provide cgtqmx6eval board its own variant of ddr setup config file. Move board/freescale/imx/ddr/ mx6q_4x_mt41j128.cfg to board/freescale/mx6sabresd/ as this is was designed for the mx6sabresd board. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-09-22-324/+1674
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| * | imx: Fix warning by building vf610twr_nandStefano Babic2014-09-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit d6d07a9b... arm: vf610: add NAND support for vf610twr generates the following warnings: WARNING: no status info for 'vf610twr_nand' WARNING: no maintainers for 'vf610twr_nand'WARNING: no status info for 'vf610twr_nand' This is due to the fact that vf610twr_nand_defconfig has no Maintainer. This patch proposed Alison as Maintainer and fix it. Signed-off-by: Stefano Babic <sbabic@denx.de> Acked-by: Alison Wang <b18965@freescale.com> CC: Stefan Agner <stefan@agner.ch>
| * | mx6qsabreauto: Staticize when possibleFabio Estevam2014-09-16-8/+8
| | | | | | | | | | | | | | | | | | Turn all local symbols into static in order to make sparse happy. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6sxsabresd: Staticize i2c_pad_info1Fabio Estevam2014-09-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i2c_pad_info1 is only used locally, so it can be made static. Fix the following sparse warning: board/freescale/mx6sxsabresd/mx6sxsabresd.c:160:22: warning: symbol 'i2c_pad_info1' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | arm: vf610: add NAND support for vf610twrStefan Agner2014-09-16-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds NAND support for the Vybrid tower system (TWR-VF65GS10) provided by the vf610_nfc driver. Full 16-Bit bus width is supported. Also an aditional config vf610twr_nand is introduced which gets the environment from NAND. However, booting U-Boot from NAND is not yet possible due to missing boot configuration block (BCB). Signed-off-by: Stefan Agner <stefan@agner.ch>
* | | vf610twr: Tune DDR initialization settingsAnthony Felice2014-10-07-34/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice <tony.felice@timesys.com> [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner <stefan@agner.ch>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-26-4/+100
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| * | | board/ls1021aqds: Add DDR4 supportYork Sun2014-09-25-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
| * | | ARMv8/ls2085a: Enable secondary coresYork Sun2014-09-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| * | | ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory blockYork Sun2014-09-25-3/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: York Sun <yorksun@freescale.com>
| * | | board/ls2085a: Update env_addr after NOR flash relocationPrabhakar Kushwaha2014-09-24-0/+6
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2085a has 2 regions in system memory map. Region1 is default map from where system boots. Once u-boot is moved to DDR, IFC is re-mapped to Region2. So, update gd->env_addr to reflect correct address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-09-26-11/+46
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| * | | board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-24-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
| * | | powerpc/t104xrdb: Set DDR ODT to 75ohmPriyanka Jain2014-09-24-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR-ODT require cfg_dram_type switch set properly as per DDR type. T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type should be set to OFF for DDR3L Update t104xrdb/README for switch setting Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t104xrdb: Add T1042RDB board supportvijay rai2014-09-24-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042RDB is a Freescale reference board that hosts the T1042 SoC (and variants). The board is similar to T1040RDB, T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). T1042RDB is configured with serdes protocol 0x86 which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 DTSEC1, DTSEC2 are not connected on board. This Patch - add T1042RDB support - updates README file for T1042RDB details and update commands for switching to alternate banks from vBank0 to vBank4 and vice versa This patch also does minor clean ups for fdt defines for T1042RDB and T1042RDB_PI board Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t104xrdb: Add Support of rcw for T1042RDB in u-bootvijay rai2014-09-24-4/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support of rcw for T1042RDB, it makes following changes : - Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB - Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates comments for valid serdes protocol which is 0x06 - Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-1/+1
| | | | | | | | | | | | | | | | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | MAINTAINERS: comment out blank M: fieldMasahiro Yamada2014-09-24-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit ddaf5c8f3030050fcd356a1e49e3ee8f8f52c6d4 (patman: RunPipe() should not pipe stdout/stderr unless asked), Patman spits lots of "Invalid MAINTAINERS address: '-'" error messages for patches with global changes. It takes too long for Patman to process them. Anyway, "M: -" does not carry any important information. Rather, it is just like a place holder in case of assigning a new board maintainer. Let's comment out. This commit can be reproduced by the following command: find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | MAINTAINERS: comment out invalid maintainersMasahiro Yamada2014-09-24-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "S: Orphan" in MAINTAINERS means that the maintainer in the "M:" field is unreachable (i.e. the email address is not working). (Refer to the definition of "Orphan" adopted in U-Boot in the log of commit 31f1b654b2f395b69faa5d0d3c1eb0803923bd3b, "boards.cfg: move boards with invalid emails to Orphan") For patch files adding global changes, scripts/get_maintainer.pl adds bunch of such invalid email addresses, which results in tons of annoying bounce emails. This commit can be reproduced by the following command: find . -name MAINTAINERS | xargs sed -i -e ' /^M:[[:blank:]]/ { N /S:[[:blank:]]Orphan/s/^/#/ } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 14:17:56 +0000