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* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-125/+405
|\ \ | | | | | | | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * | powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPLYing Zhang2014-02-24-72/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the previous patches, we introduced the SPL/TPL fraamework. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t2081qds: Add T2081 QDS board supportShengzhou Liu2014-02-24-53/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T2081 QDS is a high-performance computing evaluation, development and test platform supporting the T2081 QorIQ Power Architecture processor. T2081QDS board Overview ----------------------- - T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz - 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC) - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving - Ethernet interfaces: - Two on-board 10M/100M/1G bps RGMII ports - Two 10Gbps XFI with on-board SFP+ cage - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card - Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC - SerDes: - 8 lanes up to 10.3125GHz - Supports SGMII, HiGig, XFI, XAUI and Aurora debug, - IFC: - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) - USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - PCIe: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - eSDHC: - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and voltage translators - I2C: - Four I2C controllers. - UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | common: Add get_effective_memsize() to memsize.cYork Sun2014-02-21-3/+3
| |/ |/| | | | | | | | | | | | | | | This function has been around for powerpc. It is used for systems with memory more than CONFIG_MAX_MEM_MAPPED. In case of non-contiguous memory, this feature can limit U-boot to one block without going over the limit. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-20-1/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile drivers/net/npe/Makefile These two conflicts arise from commit 0b2d3f20 ("ARM: NET: Remove the IXP NPE ethernet driver") and are resolved by deleting the drivers/net/npe/Makefile file and removing the CONFIG_IXP4XX_NPE line from Makefile.
| * | Move #ifdef(CONFIG_DISPLAY_CPUINFO) from caller to calleeMasahiro Yamada2014-02-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - When CONFIG_DISPLAY_CPUINFO is not enabled, print_cpuinfo() should be defined as an empty function in a header, include/common.h - Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif from caller, common/board_f.c and arch/arm/lib/board.c - Remove redundant prototypes in arch/arm/lib/board.c, arch/arm/include/asm/arch-am33x/sys_proto.h and board/nokia/rx51/rx51.h, keeping the one in include/common.h - Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition where it is missing Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | kbuild: add dummy obj-y to create built-in.oMasahiro Yamada2014-02-19-1/+4
| |/ | | | | | | | | | | | | | | | | We are going to switch over to Kbuild in upcoming commits. Each makefile must have non-empty obj- or obj-y to generate built-in.o on Kbuild. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-19-77/+59
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| * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-02-11-110/+346
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| * | mx6qsabreauto: Update imximage.cfgFabio Estevam2014-02-11-77/+59
| | | | | | | | | | | | | | | | | | Use the latest DDR and clock settings as the one from Freescale BSP. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | powerpc/t104xrdb: Add basic ethernet supportPriyanka Jain2014-02-03-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This covers only non-L2 switch ethernet interfaces i.e. RGMII and SGMII interface for both T1040RDB and T1042RDB_PI T1040RDB is configured as serdes protocol 0x66 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 1 SGMII on DTSEC3 T1042RDB_PI is configured as serdes protocol 0x06 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change in commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | | boards/t1040qds: Adds ethernet support for T1040Prabhakar Kushwaha2014-02-03-0/+494
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | | powerpc/mpc85xx:Fix README to show correct flash memory mapPrabhakar Kushwaha2014-02-03-6/+6
| |/ |/| | | | | | | | | | | | | | | | | | | | | Due to increased size of u-boot, FMAN ucode start address has been shifted by 256KB causing a overlap with rootfs start address. Update rootfs start address to reflect correct memory map. Also fix minor typo in README Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | eSDHC: Calculate envaddr accroding to the address formatHaijun.Zhang2014-01-22-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the 32-bit source address specifies the memory address in block address format. Block length is fixed to 512 bytes as per the SD High Capacity specification. So we need to convert the block address format to byte address format to calculate the envaddr. If there is no enough space for environment variables or envaddr is larger than 4GiB, we relocate the envaddr to 0x400. The address relocated is in the front of the first partition that is assigned for sdboot only. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx:Increase binary size for P, B & T series boards.Prabhakar Kushwaha2014-01-21-40/+40
| | | | | | | | | | | | | | | | | | | | | | u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | t2080qds/ddr: update ddr parametersShengzhou Liu2014-01-21-49/+28
| | | | | | | | | | | | | | | | | | | | | | - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s. - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are unrelated to DDR3/3L. Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPLPo Liu2014-01-21-2/+168
| | | | | | | | | | | | | | | | | | | | | | | | Using the TPL/SPL method to booting from 8k page NAND flash. - Add 256kB size SRAM tlb for second step booting; - Add spl.c for TPL image boot; - Add spl_minimal.c for minimal SPL image; - Add C29XPCIE_NAND configure; - Modify C29XPCIE.h for nand config and enviroment; Signed-off-by: Po Liu <Po.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/t2080qds: some update for t2080qdsShengzhou Liu2014-01-21-9/+69
| | | | | | | | | | | | | | | | | | | | - add more serdes protocols support. - fix some serdes lanes route. - fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d. - correct boot location info for SD/SPI boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/t1040qds: Update DDR initialization related settingsPriyanka Jain2014-01-21-10/+12
|/ | | | | | | | | | | | | | | | | | Update following DDR related settings for T1040QDS -Correct number of chip selects to two as t1040qds supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Reduced I2C speed to 50KHz as DDR-SPD does not get reliably read at 400KHz. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and 1600MT/s. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-15-1/+1
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| * mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()Fabio Estevam2014-01-15-1/+1
| | | | | | | | | | | | | | | | | | | | Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | Merge 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-14-28/+5
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| * mx6slevk: Return from cpu_eth_init() directlyFabio Estevam2014-01-13-9/+1
| | | | | | | | | | | | | | | | | | | | There is no need to print an error message when cpu_eth_init() fails because net/eth.c already prints it. In order to simplify the code, just return the value from cpu_eth_init(bis) directly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Return from cpu_eth_init() directlyFabio Estevam2014-01-13-7/+1
| | | | | | | | | | | | | | | | | | | | There is no need to print an error message when cpu_eth_init() fails because net/eth.c already prints it. In order to simplify the code, just return the value from cpu_eth_init(bis) directly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6qsabreauto: Return from cpu_eth_init() directlyFabio Estevam2014-01-13-7/+1
| | | | | | | | | | | | | | | | | | | | There is no need to print an error message when cpu_eth_init() fails because net/eth.c already prints it. In order to simplify the code, just return the value from cpu_eth_init(bis) directly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6qarm2: Remove unneeded error message when cpu_eth_init() failsFabio Estevam2014-01-13-5/+2
| | | | | | | | | | | | | | There is no need to print an error message when cpu_eth_init() fails because net/eth.c already prints it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-10-626/+170
|\ \ | |/ | | | | | | | | | | | | | | | | Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-626/+170
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| | * mx6sabresd: Fix LVDS width and color formatFabio Estevam2013-12-17-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | mx6sabresd boards have a 18-bit LVDS data width and the correct color format is RGB666. Suggested-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6sabresd: Allow probing HSYNC, VSYNC and DISP_CLK signalsFabio Estevam2013-12-17-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging. Configure them as active pins. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * MX6 SabreSD: Use readl() to read the CCM_CCGR3 registerLiu Ying2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Align with the context to use readl() to read the CCM_CCGR3 register with memory barrier instead of __raw_readl(). Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * i.MX6 (DQ/DLS): use macros for mux and pad declarationsEric Nelson2013-12-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include <asm/arch/mx6-pins.h> with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * imx: Explicitly pass the I2C bus number in pmic_init()Fabio Estevam2013-12-17-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pmic_init() function has the I2C or SPI bus number that is connected to the PMIC. Instead of passing I2C_PMIC, explicitly pass the I2C bus number via I2C_x definition. The motivation for doing this is to avoid people just doing a copy and paste of I2C_PMIC into their board file when another I2C bus is actually used to interface to their PMIC. This also makes more obvious which is the I2C bus connected to the PMIC, without having to search in the source code for the meaning of the 'I2C_PMIC' number. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * mx6sabresd: Add SPI NOR supportFabio Estevam2013-11-28-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port. Add support for it. This patch allows the SPI NOR flash to be succesfully detected: => sf probe SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6sabresd: Fix wrong colors in LVDS splashFabio Estevam2013-11-28-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently HDMI splash screen is selected by default on mx6sabresd boards. As LVDS is also enabled, this causes incorrect colors to be displayed im the LVDS panel. Fix this by selecting the LVDS panel as the default splash output and only keep HDMI or LVDS turned on at the same time. Acked-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx31pdk: Fix pmic_init() argumentFabio Estevam2013-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On mx31pdk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx51evk: Fix pmic_init() argumentFabio Estevam2013-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx51evk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * i.MX6DQ/DLS: replace pad names with their Linux kernel equivalentsEric Nelson2013-11-13-108/+108
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * mx6: titanium: Move BSP code to barco board directoryStefan Roese2013-11-13-499/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the titanium board is not a Freescale board, move its BSP code from the freescale board directory to the newly created barco board directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Korsgaard <peter.korsgaard@barco.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Peter Korsgaard <peter.korsgaard@barco.com>
| | * titanium: Return the error when cpu_eth_init() failsFabio Estevam2013-11-13-1/+1
| | | | | | | | | | | | | | | | | | | | | When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
* | | board/t1040qds: Enable memory reset controlPrabhakar Kushwaha2014-01-02-0/+5
| | | | | | | | | | | | | | | | | | | | | Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start accessing it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | | powerpc/b4860/pbl: fix rcw cfgShaohui Xie2014-01-02-1/+1
| | | | | | | | | | | | | | | | | | The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* | | board/freescale:Remove use of CONFIG_SPL_NAND_MINIMALPrabhakar Kushwaha2014-01-02-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary review purpose. So, use CONFIG_SPL_NAND_BOOT config. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | | board/t1040qds: Fix typo in t1040_pbi.cfg filePrabhakar Kushwaha2014-01-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | T1040QDS has 256KB SRAM. Comment is showing wrong information. So update the comment. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | | Makefile: delete unnecessary CPPFLAGS settingsMasahiro Yamada2013-12-13-2/+0
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | powerpc/p1_p2_rdb_pc: Fix warnings for __iomem pointersClaudiu Manoil2013-12-11-2/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the __iomem address space marker for the tsec pointers to struct tsec_mii_mng memory mapped register regions. This solves the sparse warnings for mixig normal pointers with __iomem pointers for tsec. p1_p2_rdb_pc.c:373:24: warning: incorrect type in assignment (different address spaces) p1_p2_rdb_pc.c:373:24: expected struct tsec_mii_mng [noderef] <asn:2>*regs p1_p2_rdb_pc.c:373:24: got struct tsec_mii_mng *<noident> Use TSEC_GET_MDIO_REGS_BASE() for the remaining mdio 'regs' initializations to remove the __iomem warnings and for consistency. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-12-10-9/+9
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: board/samsung/trats2/trats2.c include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-10-175/+2418
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * | | arm: keep all sections in ELF fileAlbert ARIBAUD2013-12-07-9/+9
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Current LDS files /DISCARD/ a lot of sections when linking ELF files, causing diagnostic tools such as readelf or objdump to produce partial output. Keep all section at link stage, filter only at objcopy time so that .bin remains minimal. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | | powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROMPo Liu2013-12-04-0/+13
| |/ |/| | | | | | | | | | | | | | | | | Currently, there is only one EEPROM on c29xpcie board which is AT24C1024. We program the SPD data at beginning of the AT24C1024.But the AT24C1024 has a 16-bit sub-address mode. This patch is tomake it work when getting SPD in a 16-bit sub-address EEPROM. Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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