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| * powerpc: P2041RDB: Remove macro CONFIG_P2041RDBYork Sun2016-11-23-1/+1
| | | | | | | | | | | | Use CONFIG_TARGET_P2041RDB instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1_P2_RDB_PC: Drop TARGET_P1_P2_RDB_PCYork Sun2016-11-23-2/+1
| | | | | | | | | | | | | | All boards covered by this group have been converted to their own targers. Drop TARGET_P1_P2_RDB_PC from Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P2020RDB-PC: Separate from P1_P2_RDB_PC in KconfigYork Sun2016-11-23-2/+3
| | | | | | | | | | | | | | | | | | Use TARGET_P2020RDB_PC instead of sharing with P1_P2_RDB_PC to simplify Kconfig and config macros. Remove macro CONFIG_P2020RDB. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1025RDB: Separate from P1_P2_RDB_PC in KconfigYork Sun2016-11-23-6/+7
| | | | | | | | | | | | | | | | | | Use TARGET_P1025RDB instead of sharing with P1_P2_RDB_PC to simplify Kconfig and config macros. Remove macro CONFIG_P1025RDB. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1024RDB: Separate from P1_P2_RDB_PC in KconfigYork Sun2016-11-23-2/+3
| | | | | | | | | | | | | | | | | | Use TARGET_P1024RDB instead of sharing with TARGET_P1_P2_RDB_PC to simplify Kconfig and macros. Remove macro CONFIG_P1024RDB. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1021RDB: Separate from P1_P2_RDB_PC in KconfigYork Sun2016-11-23-8/+9
| | | | | | | | | | | | | | | | | | Use TARGET_P1021RDB instead of sharing with TARGET_P1_P2_RDB_PC to simplify Kconfig and macros. Remove macro CONFIG_P1021RDB. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1020UTM: Separate from P1_P2_RDB_P2 in KconfigYork Sun2016-11-23-2/+3
| | | | | | | | | | | | | | | | | | Use TARGET_P1020UTM instead of sharing with TARGET_P1_P2_RDB_PC to simplify Kconfig and config macros. Remove macro CONFIG_P1020UTM. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1020RDB-PD: Separate from P1_P2_RDB_PC in KconfigYork Sun2016-11-23-5/+6
| | | | | | | | | | | | | | | | | | Use TARGET_P1020RDB_PD instead of sharing with P1_P2_RDB_PC to simplify Kconfig and config macros. Remove macro CONFIG_P1020RDB_PD. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1020RDB-PC: Separate from P1_P2_RDB_PC in KconfigYork Sun2016-11-23-5/+6
| | | | | | | | | | | | | | | | | | Use TARGET_P1020RDB_PC instead of sharing with TARGET_P1_P2_RDB_PC to simplify Kconfig and config macros. Remove macro CONFIG_P1020RDB_PC. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1020MBG: Separate from P1_P2_RDB_PC in KconfigYork Sun2016-11-23-4/+5
| | | | | | | | | | | | | | | | | | Use TARGET_P1020MBG instead of sharing with TARGET_P1_P2_RDB_PC to simplify Kconfig and other macros. Remove macro CONFIG_P1020MBG. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1022DS: Remove macro CONFIG_P1022DSYork Sun2016-11-23-1/+1
| | | | | | | | | | | | Use CONFIG_TARGET_P1022DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: P1010RDB: Remove macros CONFIG_P1010RDB_PA and CONFIG_P1010RDB_PBYork Sun2016-11-23-12/+12
| | | | | | | | | | | | | | Remove CONFIG_P1010RDB_PA and CONFIG_P1010RDB_PB and split TARGET_P1010RDB to TARGET_P1010RDB_PA and TARGET_P1010RDB_PB in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8572DS: Remove macro CONFIG_MPC8572DSYork Sun2016-11-23-2/+2
| | | | | | | | | | | | Use CONFIG_TARGET_MPC8572DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8569MDS: Remove macro CONFIG_MPC8569MDSYork Sun2016-11-23-1/+1
| | | | | | | | | | | | Use CONFIG_TARGET_MPC8569MDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8555CDS: Remove macro CONFIG_MPC8555CDSYork Sun2016-11-23-1/+1
| | | | | | | | | | | | Use CONFIG_TARGET_MPC8555CDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8541CDS: Remove macro CONFIG_MPC8541CDSYork Sun2016-11-23-1/+1
| | | | | | | | | | | | Replace with CONFIG_TARGET_MPC8541CDS from Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8536DS: Remove macro CONFIG_MPC8536DSYork Sun2016-11-23-2/+2
| | | | | | | | | | | | Use CONFIG_TARGET_MPC8536DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8544DS: Remove macro CONFIG_MPC8544DSYork Sun2016-11-23-1/+1
| | | | | | | | | | | | Use CONFIG_TARGET_MPC8544DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8548CDS: Remove macro CONFIG_MPC8548CDSYork Sun2016-11-23-1/+1
| | | | | | | | | | | | Use CONFIG_TARGET_MPC8548CDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* | armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain2016-11-22-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: ls1021a: improve the core frequency to 1.2GHZYuan Yao2016-11-21-7/+7
| | | | | | | | | | | | | | Change core clock to 1.2GHz in the configurations for SD and NAND boot. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls2080aqds: fix SGMII repeater settingsShaohui Xie2016-11-21-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | The current value to check whether the PHY was configured has dependency on MC, it expects MC to start PCS AN, this is not true during boot up, so it should be changed to remove the dependency. The PHY's register space should be restore to default after accessing extended space. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls2080a: Update serdes protocol supportPriyanka Jain2016-11-21-3/+119
| | | | | | | | | | | | | | | | | | | | | | | | Add these serdes protocols Serdes1: 0x39, 0x4B, 0x4C, 0x4D Serdes2: 0x47, 0x57 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [YS: Revise commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls1046aqds: add lpuart supportShaohui Xie2016-11-21-0/+18
| | | | | | | | | | | | | | LPUART0 is used by default, and it's using platform clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv7: Add support of ls1021a-iot boardFeng Li2016-11-21-0/+464
|/ | | | | | | | The patch adds support for Freescale ls1021a-iot board. Signed-off-by: Feng Li <feng.li_2@nxp.com> [YS: rewrite commit message, fix whitespace in Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
* ls2080ardb: Reserve DP-DDR RAMAlexander Graf2016-11-17-0/+9
| | | | | | | | The DP-DDR shouldn't be exposed as conventional memory to an OS, so let's rather claim it's a reserved region in the EFI memory map Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
* ls2080: Exit dpaa only right before exiting U-BootAlexander Graf2016-11-17-13/+15
| | | | | | | | | | | | | | | | | | | | | On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> [agraf: Fix x86 build]
* mx6ull_14x14_evk: Add README fileDiego Dorta2016-11-13-0/+36
| | | | | | | | | Add a README file to help users getting started with the board. Signed-off-by: Diego Dorta <diego.dorta@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mx6sabresd: Make Ethernet functional againFabio Estevam2016-11-06-0/+33
| | | | | | | | | | | | | | | | | Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate config for AR8031") ethernet does not work on mx6sabresd. This commit correctly assigns ar8031_config() as the configuration function for AR8031 in the same way as done in the Linux kernel. However, on mx6sabresd design we need some additional configuration, such as enabling the 125 MHz AR8031 output that needs to be done in the board file. This also aligns with the same method that the kernel performs the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-28-9/+263
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: common/Kconfig configs/dms-ba16_defconfig
| * imx: s/docs\/README.imximage/doc\/README.imximage/gJagan Teki2016-10-26-6/+6
| | | | | | | | | | | | | | | | | | | | Fixed typo for doc/README.imximage on respective imximage.cfg files. Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx: mx6ullevk: correct boot device macroPeng Fan2016-10-24-2/+2
| | | | | | | | | | | | | | | | Correct boot device macro according to kconfig entry in common/Kconfig Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6ullevk: support pluginPeng Fan2016-10-24-1/+140
| | | | | | | | | | | | | | | | Add plugin code for mx6ullevk. Define CONFIG_USE_IMXIMG_PLUGIN in defconfig file to use plugin code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * mx6sabresd: Add README fileDiego Dorta2016-10-17-0/+103
| | | | | | | | | | | | | | | | | | Add a README to explain the steps for booting mx6sabresd in different ways: 1. Booting via Normal U-Boot (u-boot.imx) 2. Booting via SPL (SPL and u-boot.img) 3. Booting via Falcon mode (SPL launches the kernel directly) Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
| * mx6sabresd: Add Falcon mode supportDiego Dorta2016-10-17-0/+12
| | | | | | | | | | | | | | | | Allow i.MX6Q Sabre SD to load the kernel and dtb via SPL in Falcon mode. Based on the Falcon mode code for MX6 Gateworks Ventana board. Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
* | pbl: use "wait" command instead of "flush" commandZhao Qiang2016-10-14-8/+4
| | | | | | | | | | | | | | | | | | | | PBL flush command is restricted to CCSR memory space. So use WAIT PBI command to provide enough time for data to get flush in target memory. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> [York Sun: rewrap commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* | Txxx/RCW: Split unified RCW to RCWs for sd, spi and nand.Zhao Qiang2016-10-14-2/+217
|/ | | | | | | | | | | | | T series boards use unified RCW for sd, spi and nand boot. Now split txxx_rcw.cfg to txxx_sd_rcw.cfg, txxx_spi_rcw.cfg and txxx_nand_rcw.cfg for SPI/NAND/SD boot. And modify RCW[PBI_SRC] for them: PBI_SRC=5 for SPI 24-bit addressing PBI_SRC=6 for SD boot PBI_SRC=14 for IFC NAND boot Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-10-12-38/+26
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1021aqds.h include/configs/ls1021atwr.h
| * armv7: LS1021a: enable i-cache in start.SXiaoliang Yang2016-10-06-0/+12
| | | | | | | | | | | | | | | | | | | | Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First stage of u-boot can run faster after that. There is a description about skip lowlevel init in board/freescale/ls1021atwr/README. Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl_sec_mon: Update driver for Security MonitorSumit Garg2016-10-06-38/+14
| | | | | | | | | | | | | | | | | | | | | | Update the API's for transition of Security Monitor states. Instead of providing both initial and final states for transition, just provide final state for transition as Security Monitor driver will take care of it internally. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> [York Sun: Reformatted commit message slightly] Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-08-154/+436
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| * | arm: imx: add i.MX6ULL 14x14 EVK board supportPeng Fan2016-10-04-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6ULL EVK board support: Add device tree file, which is copied from NXP Linux. Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR. The uart iomux settings are still keeped in board file. Boot Log: U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800) CPU: Freescale i.MX6ULL rev1.0 at 396MHz CPU: Commercial temperature grade (0C to 95C) at 15C Reset cause: POR Model: Freescale i.MX6 ULL 14x14 EVK Board Board: MX6ULL 14x14 EVK DRAM: 512 MiB MMC: initialized IMX pinctrl driver FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 => mmc dev 1 switch to partitions #0, OK mmc1 is current device Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | mx6sabresd: Make SPL DDR configuration to match the DCD tableFabio Estevam2016-10-04-154/+197
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. This causes stability issues like the ones reported at 7dbda25ecd6d7c ("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also: http://lists.denx.de/pipermail/u-boot/2016-September/266355.html . As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Retrieved the DCD tables from: board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg and board/freescale/mx6sabresd/mx6qp.cfg (NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga) This method makes it easier for people converting from non-SPL to SPL code. Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* | spi: Move freescale-specific code into a private headerSimon Glass2016-10-06-18/+39
|/ | | | | | | | | | | | | | At present there are two SPI functions only used by freescale which are defined in the spi_flash.h header. One function name matches an existing generic SPL function. Move these into a private header to avoid confusion. Arcturus looks like it does not actually support SPI, so drop the SPI code from that board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* usb: fsl: Rename fdt_fixup_dr_usbSriram Dash2016-09-27-26/+26
| | | | | | | | The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-427/+2011
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun2016-09-26-3/+51
| | | | | | | | | | | | | | | | | | Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046aqds: Add LS1046AQDS board supportShaohui Xie2016-09-14-4/+1084
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046ardb: Add LS1046ARDB board supportMingkai Hu2016-09-14-0/+751
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-348/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-09 13:45:23 +0000