summaryrefslogtreecommitdiff
path: root/board/freescale
Commit message (Collapse)AuthorAgeLines
* ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun2014-07-04-0/+356
| | | | | | | | | | | | | | | | LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-30-3/+233
|\
| * mx28evk: Add documentation on how to boot from SPI NORFabio Estevam2014-06-17-3/+19
| | | | | | | | | | | | | | | | | | Explain the necessary steps in order to boot from SPI NOR. Based on a earlier submission from Mårten Wikman. Signed-off-by: Mårten Wikman <marten.wikman@novia.fi> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabred: Add PFUZE100 PMIC supportFabio Estevam2014-05-28-0/+84
| | | | | | | | | | | | | | | | mx6sabresd boards have a PFUZE100 PMIC connected to I2C2 bus. Add support for it Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabreauto: Add the mx6dual-lite variantFabio Estevam2014-05-28-0/+130
| | | | | | | | | | | | Tested by booting a mainline kernel via TFTP. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-25-1068/+92
|\ \
| * | freescale: m5253demo: fix unused-but-set-variable warningsMasahiro Yamada2014-06-19-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following warning messages: In function 'flash_erase': 180:21: warning: variable 'last' set but not used [-Wunused-but-set-variable] In function 'write_buff': 322:10: warning: variable 'port_width' set but not used [-Wunused-but-set-variable] Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | mx31ads: Fix the U-Boot binary outputSimon Glass2014-06-11-1/+3
| | | | | | | | | | | | | | | | | | | | | Correct the binary output so that image_binary_size is really at the end of the image. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-06-05-28/+87
| |\ \
| | * | powerpc/B4420: Fixed incomplete handling for 0x9d serdes2poonam aggrwal2014-06-05-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Crossbars and IDT were not getting configured for Serdes2 protocol 0x9d for B4420. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | powerpc/t4rdb: Add alternate serdes protocols to align with A-007186Chunhe Lan2014-06-05-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols only using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. Alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | board/t2080qds: some update for ddrShengzhou Liu2014-06-05-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add support for 2nd DIMM slot. - make it work with DIMM which is less than 2GB. Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | powerpc/t4qds: Add alternate serdes protocols to align with A-007186Shaohui Xie2014-06-05-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | board/t208x: update t2080qds/t2080rdb for errata A-007186Shengzhou Liu2014-06-05-9/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As errata A-007186, we need to use the alternate serdes protocol instead of those impacted protocols. - add support for serdes protocols: 0x1b, 0x50, 0x5e, 0x64, 0x6a, 0xd2, 0x67, 0x70. - update t2080_rcw.cfg to adapt to new rcw_66_15 for t2080qds and t2080rdb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | nand_spl: remove P1023RDS_NAND supportMasahiro Yamada2014-06-05-7/+0
| |/ / | | | | | | | | | | | | | | | | | | Commit 3d5a335c announced that all the nand_spl boards would be removed before v2014.07 release. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | powerpc: mpc8260ads: remove orphan boardMasahiro Yamada2014-05-30-1028/+0
| |/ | | | | | | | | | | | | | | | | | | | | This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denx <wd@denx.de>
* | arm: vf610: Add QSPI support for VF610TWRChao Fu2014-06-09-2/+27
|/ | | | | | | Add QSPI support for VF610TWR, such as clock and iomux. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
* arm: vf610: add DDR_SEL_PAD_CONTR registerStefan Agner2014-05-25-1/+2
| | | | | | | | Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual. Signed-off-by: Stefan Agner <stefan@agner.ch>
* Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2014-05-20-19/+1491
|\ | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatting (commit 1b37fa83).
| * board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPLPrabhakar Kushwaha2014-05-16-13/+267
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the earlier patches, the SPL/TPL fraamework was introduced. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t104xrdb: Toggle deep sleep management signals after resumeTang Yuantian2014-05-16-0/+2
| | | | | | | | | | | | | | | | | | T104xrdb has several sleep management signals that are used for deep sleep. They are enabled by OS to enter deep sleep and should be disabled by u-boot when cores wake up. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/freescale: Move CRC32 offset in NXID v1 data formatEbony Zhu2014-05-16-3/+4
| | | | | | | | | | | | | | | | | | | | According to AN3638, CRC of NXID v1 is at the end of the 256-byte I2C memory. The wrong CRC32 offset prevents Uboot from reading system information from EEPROM. No NXID v0 is being used on Freescale boards. Signed-off-by: Ebony Zhu <b45385@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/freescale: Change the return value of mac_read_from_eeprom()York Sun2014-05-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | The return value has not been checked by its caller, until recent change of using generic board architecture. The error of this function is not critical enough to hang the system. Printing the warning message is enough to catch user's attention. U-boot should continue to boot to give user a chance to fix the EEPROM. Chaning the return value to 0 to avoid hanging in the board_init_r(). Signed-off-by: York Sun <yorksun@freescale.com>
| * PPC 85xx QEMU: Always assume 1 coreAlexander Graf2014-05-13-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only need u-boot to bother about a single core in the QEMU machine. Everything that would require additional knowledge of more cores gets handled by QEMU and passed straight into the payload we execute. Because of this setup, it would be counterproductive to enable SMP support in u-boot. We would have to rip CPUs out of already existing spin tables and respin them from u-boot. It would be a pretty big mess. So only assume we have a single core. This fixes errors about CONFIG_MP being disabled. Signed-off-by: Alexander Graf <agraf@suse.de>
| * powerpc/85xx: Add T4240RDB board supportChunhe Lan2014-05-13-0/+697
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
| * board/b4qds: VID supportShaveta Leekha2014-05-13-0/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. B4860QDS has a PowerOne ZM7300 programmable digital Power Manager which is programmed as per the value read from the fuses. Reference for this code is taken from t4qds VID implementation. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
| * board/freescale/common: ZM7300 driverShaveta Leekha2014-05-13-0/+258
| | | | | | | | | | | | | | | | | | | | | | Adds Support for PowerOne ZM7300 voltage regulator. This device is available on some Freescale Boards like B4860QDS and has to be programmed to adjust the voltage on the board. The device is accessible via I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-16-64/+23
|\ \
| * \ Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-05-15-77/+1503
| |\ \ | | |/
| * | mx6slevk: Add SPI NOR flash supportFabio Estevam2014-04-28-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6slevk has a m25p32 SPI NOR flash connected to ESCSPI port. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | mx6sabresd: use common detect_hdmiEric Benard2014-04-15-8/+0
| | | | | | | | | | | | Signed-off-by: Eric Bénard <eric@eukrea.com>
| * | mx6sabresd: use common board_video_skipEric Benard2014-04-15-56/+3
| | | | | | | | | | | | Signed-off-by: Eric Bénard <eric@eukrea.com>
* | | arm: move exception handling out of start.S filesAlbert ARIBAUD2014-05-15-0/+1
| |/ |/| | | | | | | | | | | | | Exception handling is basically identical for all ARM targets. Factorize it out of the various start.S files and into a single vectors.S file, and adjust linker scripts accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | powerpc/T4QDS: add two stage boot of nand/sdShaohui Xie2014-04-22-3/+158
| | | | | | | | | | | | | | | | | | | | | | Add support of 2 stage NAND/SD boot loader using SPL framework. PBL initialise the internal SRAM and copy SPL, this further initialise DDR using SPD and environment and copy u-boot from NAND/SD to DDR, finally SPL transfer control to u-boot. NOR uses CS1 instead of CS2 when NAND boot, fix it. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/t4240: updated RCW and PBI for rev2.0Shaohui Xie2014-04-22-17/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated the RCW for rev2.0 which uses new frequency settings as below: Clock Configuration: CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz, CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz, CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz, CCB:733.333 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz FMAN1: 733.333 MHz FMAN2: 733.333 MHz QMAN: 366.667 MHz PME: 533.333 MHz Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | board/t2080rdb: some update for t2080rdbShengzhou Liu2014-04-22-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | - update readme. - add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315 ucode from NOR/NAND/SPI/SD/REMOTE. - update cpld vbank with SW3[5:7]=000 as default vbank0 instead of previous SW3[5:7]=111 as default vbank. - fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | board/t208xrdb: Add support of 2-stage NAND/SPI/SD bootShengzhou Liu2014-04-22-16/+188
| | | | | | | | | | | | | | | | | | | | | | Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | board/t208xqds: Add support of 2-stage NAND/SPI/SD bootShengzhou Liu2014-04-22-2/+154
| | | | | | | | | | | | | | | | | | | | | | | | Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH] Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/t1040rdb: added a break in switch caseShaohui Xie2014-04-22-0/+1
| | | | | | | | | | | | | | | | There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it will fall into case PHY_INTERFACE_MODE_RGMII. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDBPrabhakar Kushwaha2014-04-22-3/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of 2 stage NAND, SD, SPI boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | board/b4qds:Add support of 2 stage NAND boot-loaderPrabhakar Kushwaha2014-04-22-3/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | T1040QDS/U-QE: Add u-qe support to t1040qdsZhao Qiang2014-04-22-0/+27
| | | | | | | | | | | | | | Add u-qe support for t1040qds Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mpc85xx: Add deep sleep support on T104xRDBTang Yuantian2014-04-22-0/+10
| | | | | | | | | | | | | | Add deep sleep support on T104xRDB platforms. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mpc85xx: Add deep sleep support on T1040QDSTang Yuantian2014-04-22-0/+12
| | | | | | | | | | | | | | Add deep sleep support on T1040QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | board/t104xrdb: Add support of CPLDPrabhakar Kushwaha2014-04-22-0/+166
| | | | | | | | | | | | | | | | | | | | | | T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mpc85xx/T1040QDS_D4: Add DDR4 supportYork Sun2014-04-22-27/+27
| | | | | | | | | | | | | | T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG. Signed-off-by: York Sun <yorksun@freescale.com>
* | board/b4860qds:Slow MDC clock to comply IEEE specs in PBI configPrabhakar Kushwaha2014-04-22-0/+3
| | | | | | | | | | | | | | | | | | | | The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC 85xx: Add qemu-ppce500 machineAlexander Graf2014-04-22-0/+357
|/ | | | | | | | | | | | | | | | For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: vf610: fix double iomux configuration for vf610twr boardMarcel Ziswiler2014-04-07-1/+0
| | | | | | Get rid of double VF610_PAD_DDR_A15__DDR_A_15 iomux configuration. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* Merge branch 'master' of git://git.denx.de/u-boot-arm into masterStefano Babic2014-04-04-264/+1638
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-10-31 11:19:37 +0000