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* board/freescale/common: ZM7300 driverShaveta Leekha2014-05-13-0/+258
| | | | | | | | | | | Adds Support for PowerOne ZM7300 voltage regulator. This device is available on some Freescale Boards like B4860QDS and has to be programmed to adjust the voltage on the board. The device is accessible via I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* powerpc/T4QDS: add two stage boot of nand/sdShaohui Xie2014-04-22-3/+158
| | | | | | | | | | | Add support of 2 stage NAND/SD boot loader using SPL framework. PBL initialise the internal SRAM and copy SPL, this further initialise DDR using SPD and environment and copy u-boot from NAND/SD to DDR, finally SPL transfer control to u-boot. NOR uses CS1 instead of CS2 when NAND boot, fix it. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t4240: updated RCW and PBI for rev2.0Shaohui Xie2014-04-22-17/+3
| | | | | | | | | | | | | | | | | | | | Updated the RCW for rev2.0 which uses new frequency settings as below: Clock Configuration: CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz, CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz, CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz, CCB:733.333 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz FMAN1: 733.333 MHz FMAN2: 733.333 MHz QMAN: 366.667 MHz PME: 533.333 MHz Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t2080rdb: some update for t2080rdbShengzhou Liu2014-04-22-6/+6
| | | | | | | | | | | | - update readme. - add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315 ucode from NOR/NAND/SPI/SD/REMOTE. - update cpld vbank with SW3[5:7]=000 as default vbank0 instead of previous SW3[5:7]=111 as default vbank. - fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t208xrdb: Add support of 2-stage NAND/SPI/SD bootShengzhou Liu2014-04-22-16/+188
| | | | | | | | | | | Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t208xqds: Add support of 2-stage NAND/SPI/SD bootShengzhou Liu2014-04-22-2/+154
| | | | | | | | | | | | Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1040rdb: added a break in switch caseShaohui Xie2014-04-22-0/+1
| | | | | | | | There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it will fall into case PHY_INTERFACE_MODE_RGMII. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDBPrabhakar Kushwaha2014-04-22-3/+256
| | | | | | | | | | | | | | Add support of 2 stage NAND, SD, SPI boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/b4qds:Add support of 2 stage NAND boot-loaderPrabhakar Kushwaha2014-04-22-3/+135
| | | | | | | | | | | | | | Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* T1040QDS/U-QE: Add u-qe support to t1040qdsZhao Qiang2014-04-22-0/+27
| | | | | | | Add u-qe support for t1040qds Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: Add deep sleep support on T104xRDBTang Yuantian2014-04-22-0/+10
| | | | | | | Add deep sleep support on T104xRDB platforms. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: Add deep sleep support on T1040QDSTang Yuantian2014-04-22-0/+12
| | | | | | | Add deep sleep support on T1040QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t104xrdb: Add support of CPLDPrabhakar Kushwaha2014-04-22-0/+166
| | | | | | | | | | | T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/T1040QDS_D4: Add DDR4 supportYork Sun2014-04-22-27/+27
| | | | | | | T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG. Signed-off-by: York Sun <yorksun@freescale.com>
* board/b4860qds:Slow MDC clock to comply IEEE specs in PBI configPrabhakar Kushwaha2014-04-22-0/+3
| | | | | | | | | | The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* PPC 85xx: Add qemu-ppce500 machineAlexander Graf2014-04-22-0/+357
| | | | | | | | | | | | | | | | For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: vf610: fix double iomux configuration for vf610twr boardMarcel Ziswiler2014-04-07-1/+0
| | | | | | Get rid of double VF610_PAD_DDR_A15__DDR_A_15 iomux configuration. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* Merge branch 'master' of git://git.denx.de/u-boot-arm into masterStefano Babic2014-04-04-264/+1638
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
| * m68k: Remove M5271EVB and idmr board supportMasahiro Yamada2014-03-10-217/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it as 1000000 and idmr.h defines it as (50000000 / 64). When compiling these two boards, a warning message is displayed: time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000 and should not be defined by platforms" [-Wcpp] There are no board maintainers for them so this commit just deletes them. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Jason Jin <Jason.jin@freescale.com>
| * powerpc/t104xrdb: Update DDR initialization related settingsPriyanka Jain2014-03-07-28/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update following DDR related settings for T1040RDB, T1042RDB_PI -Correct number of chip selects to two as t1040 supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Update ddr_raw_timing sructure corresponding to DIMM. -Set ODT to off. Typically on FSL board, ODT is set to 75 ohm, but on T104xRDB, on setting this , DDR instability is observed. Board-level debugging is in progress. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/t1040qds: Add Video - HDMI supportPriyanka Jain2014-03-07-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 has internal display interface unit (DIU) for driving video. T1040QDS supports video mode via -LCD using TI enconder -HDMI type interface via HDMI encoder Chrontel, CH7301C encoder which is I2C programmable is used as HDMI connector on T1040QDS. This patch add support to -enable Video interface for T1040QDS -route qixis multiplexing to enable DIU-HDMI interface on board -program DIU pixel clock gerenartor for T1040 -program HDMI encoder via I2C on board Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t2080rdb: Add T2080PCIe-RDB board supportShengzhou Liu2014-03-07-0/+993
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. It works in two mode: standalone mode and PCIe endpoint mode. T2080PCIe-RDB Feature Overview ------------------------------ Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus: - NOR: 128MB 16-bit NOR flash - NAND: 512MB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 Crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t208xqds: fixup for t208xqdsShengzhou Liu2014-03-07-1/+2
| | | | | | | | | | | | | | | | Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0. Fix EMI2 for t2080qds, which was caused by adding t2081qds. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/b4860: Add workaround for errata A006384 and A006475Shaveta Leekha2014-03-07-0/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to workShaveta Leekha2014-03-07-4/+3
| | | | | | | | | | | | | | | | | | | | Change setting of SerDes2 refclk2 to have the default value as it is coming on board that is 156.25MHz, for XFI to work. Also change PLL_NUM variable to the one defined in config_mpc85xx.h for B4860 and B4420. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * 85xx/b4860: Alternate serdes protocols for B4860/B4420poonam aggrwal2014-03-07-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On B4860 and B4420, some serdes protocols can be used with LC VCO as well as Ring VCO options. Addded Alternate options with LC VCO for such protocols. For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/b4860qds: Add support to make PCIe SATA work on B4860QDSShaveta Leekha2014-03-07-9/+110
| | | | | | | | | | | | | | | | | | | | | | | | 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/b4860qds: Add support to make Aurora work on B4860QDSShaveta Leekha2014-03-07-4/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add new SerDes1 protocols having Aurora in them 2) Add VSC cross point connections for Aurora to work with CPRI and SGMIIs 3) Configure VSC crossbar switch to connect SerDes1 lanes to aurora on board, by checking SerDes1 protocols 4) SerDes1 Refclks have been set properly to make Aurora, CPRI and SGMIIs to work together properly Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board: config.mk: delete unused sinclude directiveMasahiro Yamada2014-03-04-2/+0
| | | | | | | | | | | | config.tmp is not there. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * sizes.h - consolidate for all architecturesAlexey Brodkin2014-03-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copied from Linux sources "include/linux/sizes.h" commit 413541dd66d51f791a0b169d9b9014e4f56be13c Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Tom Rini <trini@ti.com> Acked-by: Stefan Roese <sr@denx.de> [trini: Add bcm Kona platforms to the patch] Signed-off-by: Tom Rini <trini@ti.com>
* | arm: mx5: Avoid hardcoding memory sizes on MX53QSBMarek Vasut2014-03-31-7/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM size can be easily detected at runtime on i.MX53. Implement such detection on MX53QSB and adjust the rest of the macros accordingly to use the detected values. An important thing to note here is that we had to override the function for trimming the effective DRAM address, get_effective_memsize(). That is because the function uses CONFIG_MAX_MEM_MAPPED as the upper bound of the available DRAM and we don't have gd->bd->bi_dram[0].size set up at the time the function is called, thus we cannot put this into the macro CONFIG_MAX_MEM_MAPPED . Instead, we use custom override where we use the size of the first DRAM block which we just detected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* | ARM: mx6: Add PCIe on SabreSDPMarek Vasut2014-03-31-0/+11
|/ | | | | | | | | | Add support for PCIe on MX6 SabreSDP board and enable the support in the config file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Liu Ying <Ying.Liu@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-02-26-2/+7
|\ | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/config.mk board/ti/am43xx/mux.c include/configs/am43xx_evm.h Signed-off-by: Tom Rini <trini@ti.com>
| * arm: make _end compiler-generatedAlbert ARIBAUD2014-02-26-2/+7
| | | | | | | | | | | | | | | | | | This prevents references to _end from generating absolute relocation records. This change is binary invariant for ARM targets. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-125/+405
|\ \ | | | | | | | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * | powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPLYing Zhang2014-02-24-72/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the previous patches, we introduced the SPL/TPL fraamework. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t2081qds: Add T2081 QDS board supportShengzhou Liu2014-02-24-53/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T2081 QDS is a high-performance computing evaluation, development and test platform supporting the T2081 QorIQ Power Architecture processor. T2081QDS board Overview ----------------------- - T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz - 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC) - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving - Ethernet interfaces: - Two on-board 10M/100M/1G bps RGMII ports - Two 10Gbps XFI with on-board SFP+ cage - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card - Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC - SerDes: - 8 lanes up to 10.3125GHz - Supports SGMII, HiGig, XFI, XAUI and Aurora debug, - IFC: - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) - USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - PCIe: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - eSDHC: - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and voltage translators - I2C: - Four I2C controllers. - UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | common: Add get_effective_memsize() to memsize.cYork Sun2014-02-21-3/+3
| |/ |/| | | | | | | | | | | | | | | This function has been around for powerpc. It is used for systems with memory more than CONFIG_MAX_MEM_MAPPED. In case of non-contiguous memory, this feature can limit U-boot to one block without going over the limit. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-20-1/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile drivers/net/npe/Makefile These two conflicts arise from commit 0b2d3f20 ("ARM: NET: Remove the IXP NPE ethernet driver") and are resolved by deleting the drivers/net/npe/Makefile file and removing the CONFIG_IXP4XX_NPE line from Makefile.
| * | Move #ifdef(CONFIG_DISPLAY_CPUINFO) from caller to calleeMasahiro Yamada2014-02-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - When CONFIG_DISPLAY_CPUINFO is not enabled, print_cpuinfo() should be defined as an empty function in a header, include/common.h - Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif from caller, common/board_f.c and arch/arm/lib/board.c - Remove redundant prototypes in arch/arm/lib/board.c, arch/arm/include/asm/arch-am33x/sys_proto.h and board/nokia/rx51/rx51.h, keeping the one in include/common.h - Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition where it is missing Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | kbuild: add dummy obj-y to create built-in.oMasahiro Yamada2014-02-19-1/+4
| |/ | | | | | | | | | | | | | | | | We are going to switch over to Kbuild in upcoming commits. Each makefile must have non-empty obj- or obj-y to generate built-in.o on Kbuild. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-19-77/+59
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| * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-02-11-110/+346
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| * | mx6qsabreauto: Update imximage.cfgFabio Estevam2014-02-11-77/+59
| | | | | | | | | | | | | | | | | | Use the latest DDR and clock settings as the one from Freescale BSP. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | powerpc/t104xrdb: Add basic ethernet supportPriyanka Jain2014-02-03-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This covers only non-L2 switch ethernet interfaces i.e. RGMII and SGMII interface for both T1040RDB and T1042RDB_PI T1040RDB is configured as serdes protocol 0x66 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 1 SGMII on DTSEC3 T1042RDB_PI is configured as serdes protocol 0x06 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change in commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | | boards/t1040qds: Adds ethernet support for T1040Prabhakar Kushwaha2014-02-03-0/+494
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | | powerpc/mpc85xx:Fix README to show correct flash memory mapPrabhakar Kushwaha2014-02-03-6/+6
| |/ |/| | | | | | | | | | | | | | | | | | | | | Due to increased size of u-boot, FMAN ucode start address has been shifted by 256KB causing a overlap with rootfs start address. Update rootfs start address to reflect correct memory map. Also fix minor typo in README Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | eSDHC: Calculate envaddr accroding to the address formatHaijun.Zhang2014-01-22-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the 32-bit source address specifies the memory address in block address format. Block length is fixed to 512 bytes as per the SD High Capacity specification. So we need to convert the block address format to byte address format to calculate the envaddr. If there is no enough space for environment variables or envaddr is larger than 4GiB, we relocate the envaddr to 0x400. The address relocated is in the front of the first partition that is assigned for sdboot only. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx:Increase binary size for P, B & T series boards.Prabhakar Kushwaha2014-01-21-40/+40
| | | | | | | | | | | | | | | | | | | | | | u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | t2080qds/ddr: update ddr parametersShengzhou Liu2014-01-21-49/+28
| | | | | | | | | | | | | | | | | | | | | | - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s. - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are unrelated to DDR3/3L. Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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