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* MX51EVK: Remove CPLD related codeFabio Estevam2010-04-17-68/+0
| | | | | | There is no CPLD on MX51EVK board, so remove CPLD related function. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* m68k: Move cpu/$CPU to arch/m68k/cpu/$CPUPeter Tyser2010-04-13-41/+41
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* arm: Move cpu/$CPU to arch/arm/cpu/$CPUPeter Tyser2010-04-13-1/+1
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-13-13/+13
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Rename lib_generic/ to lib/Peter Tyser2010-04-13-24/+24
| | | | | | | | Now that the other architecture-specific lib directories have been moved out of the top-level directory there's not much reason to have the '_generic' suffix on the common lib directory. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Move lib_$ARCH directories to arch/$ARCH/libPeter Tyser2010-04-13-29/+29
| | | | | | | | | Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk This change is intended to clean up the top-level directory structure and more closely mimic Linux's directory organization. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Create CPUDIR variablePeter Tyser2010-04-13-4/+4
| | | | | | | | | | | | The CPUDIR variable points to the location of a target's CPU directory. Currently, it is set to cpu/$CPU. However, using $CPUDIR will allow for more flexibility in the future. It lays the groundwork for reorganizing U-Boot's directory structure to support a layout such as: arch/$ARCH/cpu/$CPU/* (architecture with multiple CPU types) arch/$ARCH/cpu/* (architecture with one CPU type) Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* p2020ds: add alternate boot bank support using the ngPIXIS FPGATimur Tabi2010-04-07-35/+214
| | | | | | | | | | | | | | | The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS. The ngPIXIS has one distinct new feature: the values of the on-board switches can be selectively overridden with shadow registers. This feature is used to boot from a different NOR flash bank, instead of having a register dedicated for this purpose. Because the ngPIXIS is so different from the previous PIXIS, a new file is introduced: ngpixis.c. Also update the P2020DS checkboard() function to use the new macros defined in the header file. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: improve the PIXIS code and fix a few bugsTimur Tabi2010-04-07-168/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. Delete pixis.h, because none of the exported functions were actually being used by any other file. Make all of the functions in pixis.c 'static'. Remove "#include pixis.h" from every file that has it. Remove some unnecessary #includes. Make 'pixis_base' into a macro, so that we don't need to define it in every function. Add "while(1);" loops at the end of functions that reset the board, so that execution doesn't continue while the reset is in progress. Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where appropriate. Replace ulong/uint with their spelled-out equivalents. Remove unnecessary typecasts, changing the types of some variables if necessary. Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make it easier for specific boards to support variations in the PIXIS registers sets. No current boards appears to need this feature. Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. Apparently, "pixis_reset altbank" has never worked on this board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'next'Wolfgang Denk2010-04-01-4/+12
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| * ColdFire: Fix m54455EVB save environment bugTsiChung Liew2010-03-24-1/+1
| | | | | | | | | | | | | | | | The ATMEL flash does not have buffer write feature. Assgined buffer_size = 1, so that when there is a write to the flash will not use buffer write function. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * ColdFire: M5271EVB DRAM Bring up issueTsiChung Liew2010-03-24-2/+10
| | | | | | | | | | | | | | | | Fix proper portsize: The register for portsize is either 00b, 01b, or 1xb. The value that previous assigned is 32d. Fix DRAM bring up: insert asm("nop") for every DRAM register setup Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * ColdFire: Correct bit definitionTsiChung Liew2010-03-24-1/+1
| | | | | | | | | | | | | | Use correct definition for _MASK and _UNMASK. It was combined in the previous used and causes confusion. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* | mpc86xx: set the DDR BATs after calculating true DDR sizeTimur Tabi2010-03-30-0/+4
|/ | | | | | | | | | | | | | | | | | | | After determining how much DDR is actually in the system, set DBAT0 and IBAT0 accordingly. This ensures that the CPU won't attempt to access (via speculation) addresses outside of actual memory. On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB and kept that way. If the system has less than 2GB of memory (typical for an MPC8610 HPCD), the CPU may attempt to access this memory during speculation. The zlib code is notorious for generating such memory reads, and indeed on the MPC8610, uncompressing the Linux kernel causes a machine check (without this patch). Currently we are limited to power of two sized DDR since we only use a single bat. If a non-power of two size is used that is less than CONFIG_MAX_MEM_MAPPED u-boot will crash. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Prepare v2010.03-rc1v2010.03-rc1Wolfgang Denk2010-03-12-1/+0
| | | | | | Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* MX51: removed warnings for the mx51evkStefano Babic2010-03-07-10/+1
| | | | | | | | | | | The patch removes warnings at compile time and provides some cleanup code: - Removed comment on NAND (not yet supported) from lowlevel_init.S - Removed NFMS bit definition from imx-regs.h The bit is only related to MX.25/35 and can lead to confusion - Moved is_soc_rev() to soc specific code (removed from mx51evk.c) Signed-off-by: Stefano Babic <sbabic@denx.de>
* Add initial support for Freescale mx51evk boardStefano Babic2010-03-07-0/+649
| | | | | | | | The patch adds initial support for the Freescale mx51evk board. Network (FEC) and SD controller (fsl_esdhc) are supported. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2010-02-03-1/+2
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| * 83xx, uec: split enet_interface in two variablesHeiko Schocher2010-01-31-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | There's no sensible reason to unite speed and interface type into one variable. So split this variable enet_interface into two vars: enet_interface_type, which hold the interface type and speed. Also: add the possibility for switching between 10 and 100 MBit interfaces on the fly, when running in FAST_ETH mode. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Nand boot: Add nand boot support for MPC8569mds boardLiu Yu2010-01-27-0/+20
|/ | | | | | This patch add nand boot support for MPC8569mds board. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* ppc/85xx: Add PIB/ATM support for MPC8569mdsLiu Yu2010-01-25-1/+8
| | | | | Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-19/+19
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-01-12-1/+58
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| * mpc83xx: Add NAND boot support for MPC8315E-RDB boardsAnton Vorontsov2010-01-07-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core support for NAND booting is there already, so this patch is pretty straightforward. There is one trick though: top level Makefile expects nand_spl to be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code from mpc8313erdb boards, and so to not duplicate the code we just symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> o silence make during ln echo o update documentation o and avoid: $ ./MAKEALL MPC8315ERDB_NAND Configuring for MPC8315ERDB board... sdram.o: In function `fixed_sdram': /home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay' by renaming udelay -> __udelay in the spirit of commit 3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog support". Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc85xx: Add 4-bits eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2010-01-05-0/+14
| | | | | | | | | | | | | | | | | | Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 0" document, which describes all eSDHC pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Map boot page guarded for MP bootKumar Gala2010-01-05-3/+3
| | | | | | | | | | | | | | We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Make flash TLB entry determined at runtime on FSL boardsKumar Gala2010-01-05-4/+4
| | | | | | | | | | | | | | Rather than hard coding which TLB entry the FLASH is mapped with we can use find_tlb_idx to determine the entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on P2020 DSKumar Gala2010-01-05-7/+5
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on P1/P2 RDBKumar Gala2010-01-05-6/+4
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on MPC8572 DSKumar Gala2010-01-05-8/+6
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/86xx: Clean up MPC8610 HPCD PCI setup codeKumar Gala2010-01-05-137/+62
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8548 CDS PCI setup codeKumar Gala2010-01-05-93/+48
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8568 MDS PCI setup codeKumar Gala2010-01-05-92/+45
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8569 MDS PCI setup codeKumar Gala2010-01-05-60/+26
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8544 DS PCI setup codeKumar Gala2010-01-05-179/+70
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8536 DS PCI setup codeMingkai Hu2010-01-05-191/+66
|/ | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 5xxx, fdt: move fdt_fixup_memory() to cpu.c fileHeiko Schocher2009-12-08-1/+0
| | | | | | | | u-boot updates, before starting Linux, the memory node in the DTS. As this is a "standard" feature, move this functionality to the cpu.c file for mpc5xxx and mpc512x processors. Signed-off-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' into nextWolfgang Denk2009-12-05-13/+0
|\ | | | | | | | | | | | | | | Conflicts: board/esd/plu405/plu405.c drivers/rtc/ftrtc010.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * mpc8260: move FDT memory node fixup into common CPU code.Marcel Ziswiler2009-11-22-13/+0
| | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com> Tested-by: Heiko Schocher <hs@denx.de>
* | Generic udelay() with watchdog supportIngo van Lil2009-12-05-1/+1
|/ | | | | | | | | | | | | According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
* 86xx: Remove redundant code in initdramBecky Bruce2009-11-04-10/+0
| | | | | | | | The same code exists both inside an #ifdef and outside of it. Remove the extra code for all the 86xx boards. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"Kumar Gala2009-11-04-8/+8
| | | | | | | | | | | This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc. There isn't any need to modify the API for fsl_pci_init_port to pass the status of host/agent(end-point) status. We can determine that internally to fsl_pci_init_port. Revert the patch that makes the API change. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Configure QE USB for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+36
| | | | | | | | Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Configure QE UART for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-21/+78
| | | | | | | | | | | | To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node. Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+6
| | | | | | | | SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+1
| | | | | | | | This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add eLBC NAND support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-19/+11
| | | | | | | | Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-1/+118
| | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-8/+8
| | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data ratePoonam Aggrwal2009-10-27-2/+2
| | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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