| Commit message (Collapse) | Author | Age | Lines |
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1) Turn on ZQ calib config by default in uboot.
2) Remove one problematic statement which can cause hang issue
3) Change comment style from ; to //
Signed-off-by: Robby Cai <R63905@freescale.com>
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1) IOMUX/backlight support for CLAA WVGA LCD panel.
2) Add video mode for CLAA WVGA LCD panel.
3) Support IPU di1 interface for framebuffer.
4) Enhance IPU driver.
5) Add freescale 600x400 8BPP BMP logo.
Signed-off-by: Terry Lv <R65388@freescale.com>
Signed-off-by: Liu Ying <b17645@freescale.com>
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uart outputs messy code when kernel starts on mx51.
Change uart clock to use pll2 as source clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
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1. As we can check DDR dynamically,
remove CONFIG_EMMC_DDR_MODE in mmc.c.
2. Add config CONFIG_EMMC_DDR_PORT_DETECT
config for some boards that only some board support DDR.
Signed-off-by: Terry Lv <r65388@freescale.com>
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All type of DDRs will be affected.
ddr script is available here:
http://compass.freescale.net/livelink/livelink/open/218722501
Two key points:
1. LPDDR2 ZQ calibration is different from mDDR/DDR2,
fixed in this version(they're same before).
2. TO1.1 ZQ calibration is _NOT_ compatible with TO1.0.
U-Boot default config is for TO1.1.
Please switch off CONFIG_ZQ_CALIB option if compile for TO1.0.
Other fixes:
1. Change drive strength to 0x00200000 for all ddr types.
2. Add missed config for IOMUXC_SW_PAD_CTL_PAD_DRAM_OPEN and
IOMUXC_SW_PAD_CTL_PAD_DRAM_OPENFB.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Updated DDR2 script for ARD board from Mike Kjar:
"mx53_init_TO2_DDR2_ARD_test.inc".
Tested on TO1 and TO2 ARD.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
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script v2:
http://compass.freescale.net/livelink/livelink/219931536/
Codex_DDR2_266MHz.inc.txt?func=doc.Fetch&nodeid=219931536
Signed-off-by: Robby Cai <R63905@freescale.com>
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Merge mx50_arm2 to mx50_rdp.
Signed-off-by: Terry Lv <r65388@freescale.com>
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MX50 Add ZQ calibration support for TO1.1.1.
This need to be enabled by CONFIG_ZQ_CALIB.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Total 5 registers:
0x1400023c/244/24c/254/25c: from 0x000a1401 to 0x000a0b01
Without this patch, kernel on RDP board with Elpida DDR
is not able to boot, or not stable.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Precoding: Update DDR configuration plugin to check SI Rev
and change ROM addresses as needed.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Add nand support for mx50 rdp.
Signed-off-by: Terry Lv <r65388@freescale.com>
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This patch is to set MC13892 charge regulator output voltage
as 4.2V. It fixes a typo error for chip check and makes TO3
VCC and VDDA voltages keep sync with the spec.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Support new DDR script entitled
"Rita_TO2_init_DDR2_CPU2_CMOS_TEST_CAL_v1.inc" for DDR2
boards including MX53 EVK, ARD, and ARM2 CPU2. These new settings
did not apply to TO1. Therefore, changed the DCD
for these boards to a plugin so that TO1 and TO2 can both
be supported using conditional execution of new DDR settings.
During bootup on TO2, DDR frequency is required to be below
400 MHz. Therefore, BOOT_CFG2[4] must be set to enable DDR at
333 MHz in ROM on all boards. Uboot determines silicon version
and for TO2 boosts the VCC and VDDA voltages to 1.3V, after
which the DDR frequency is also increased to 400 MHz.
This requirement meant that uboot does not calibrate PLL2
anymore until the voltage is increased. Removed the calibration
from lowlevel_init.S and from all mx53 include/configs files.
Also required that during config_periph_clk(), only CBCMR register
is touched to set source PLL. Other changes to CBCDR were removed.
Switching to PLL2 bypass clk during reprogram was also removed.
All these changes are required to increase DDR frequency to 400 MHz.
DDR2 CPU2 board with TO1 requires the following hw cfgs:
JP3 populated, and J8 set to 2-3.
For DDR2 CPU2 board with TO2, both these jumpers should be
depopulated.
ARM2 CPU3 (with DDR3) DDR configurations were not changed.
TO1 and TO2 can run well using existing DDR3 script. However,
DCD was converted to plugin to align with other boards.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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mfgtools and sb_loader can download plug-in and run plug-in
to initilize DRAM.
Signed-off-by: Frank Li <frank.li@freescale.com>
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Support nand basic read/write in MX28 u-boot.
Signed-off-by: Frank Li <frank.li@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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It should add stop usb operation for mx50 rdp,
otherwise, the usb enumeration at kernel will be very slow
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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This patch is used to fix the issue caused by ENGR00132709.
NFC_CLK definition should be used in cmd_clk interface.
MXC_NFC_CLK should be used as internal clock name.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Add "clk nfc" command support.
Limit NFC MAX clock as 34MHZ to be compatible with
some old NAND flashes.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Add NAND support for MX53 EVK and ARD.
Need to use kobs-ng to flash U-Boot on MX53 TO1. Because
MX51 TO1 ROM doesn't support bi swap solution and kernel
enable bi swap, Must enable "ignore bad block" option when
flashing U-Boot. The step is as following:
echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad
kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin
echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad
Since default configuration stores environment into SD
card and U-Boot uses get_mmc_env_devno (Read SBMR register)
to get MMC/SD slot information, you must insert SD card to
bottom SD slot to get/store environment if you are using NAND
boot on MX53 EVK.
You must config boot dip setting well when doing NAND boot.
For example, if you are using NAND 29F32G080AA NAND chip on
MX53 EVK, you can set boot dips as the following for NAND
boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on.
Other dips are off.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Update uboot LPDDR2 init code with the following changes
from latest script (v04) from Marek Xu:
http://compass.freescale.net/doc/220496654/Codex_LPDDR2_266MHz.inc.txt
1. Driver strength changed to 0x00180000 from 0x00200000
2. Memory type value changed to 0x04000000 from 0x02000000
3. New ZQ calibration entries with delay between load PU/PD and clear
4. Register at memory location 0x14000024 changed to 0x0048D005
from 0x0048EB05
Signed-off-by: Anish Trivedi <anish@freescale.com>
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This change make a bootable default setting of MX53 EVK and MX51 BBG board,
the old default setting is too old to boot android system up.
Also add the recovery command in the env strings, if you want
to boot to recovery mode with mx53_evk, you can just :
> run bootcmd_android_recovery
This command will boot android into recovery mode.
Also fix MX51 can't see UI in recovery mode.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add support for building uboot for MX50 reference design platform:
1) LPDDR2 init script (v0.3 from Mike Kjar, dated 9/14)
2) iomux
3) new board file and machine id for RDP
4) Updates for iram boot on RDP
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Use serial_mxc as uart driver for all platforms.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix typo error for MX53 recovery mode.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Add MX53 Automotive Reference Board (ARD) support
1. Add DDR2 initialization script
2. Add external ethernet support
3. Update PIN settings for UART, I2C, SDHC etc
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Rename the folder "mx53_evk" as "mx53_rd" to put
all MX53 board files.
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Lily Zhang <r58066@freescale.com>
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iram boot don't work.
The reason is that ivt plugins copy too much data
than that iram can hold.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add android recovery mode support for mx53.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add gpmi nfc and apbh dma support for mx50.
Signed-off-by: Terry Lv <r65388@freescale.com>
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add DDR2 support for U-BOOT.
The infomation about the init script:
Date : Aug-30,2010
Author : Tommy
Version: 0.1
please check :
http://compass.freescale.net/doc/219931536/Codex_DDR2_266MHz.inc.txt
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Move the android recovery codes into common/recovery.c.
Cut the keypad detecting time. Now we only need detect
there's POWER and HOME key pressing at the time scanning
keyboard matrix. So user must hold these two keys when bootup to
enter recovery mode. This can reduce the uboot boot time with
recovery mode configured.
Later /cache file checking for recovery command should be merged
into the common/recovery.c
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Aligned LPDDR2 initialization to the latest script
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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Update DDR script to latest according to the wiki page
http://wiki.freescale.net/pages/viewpage.action?pageId=25405083
Latest LPDDR1 (mDDR) init script can work with 200Mhz
(updated on 7/13): lpddr1_init_200MHz_size_shrink_MK.inc
Latest LPDDR2 init script can work with 266Mhz
(shrinked version and updated by Mike on July.7th):
lpddr2_init_266MHz_shrinked_tommy_MK.inc
Signed-off-by: Jason Liu <r64343@freescale.com>
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Add clk command support for mx51.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix incorrect copyright info.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add splash screen code and support for epdc.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Read mac address from fuse
Signed-off-by: Frank Li <frank.li@freescale.com>
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Add mx50 mfg firmware support
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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This is caused by fec_pwr_en pin is mis-used which lead
to FEC not power on. This commit fix this issue.
Signed-off-by:Jason Liu <r64343@freescale.com>
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1. Reconstructure fuse. Move fuse files to common directory.
2. Read mac from fuse in fec.
3. Remove scc and srk command from fuse command.
4. Change fuse to iim.
5. Add fuse for mx53.
Signed-off-by: Terry Lv <r65388@freescale.com>
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1. Adjust VDDGP voltage for 800MHZ as 1.05v.
2. Correct VDDA comments
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Add spi_get_cfg function due to the function has been made
platform specific and moved out of spi driver.
This also fix the build break for mx53 uboot
Signed-off-by:Jason Liu <r64343@freescale.com>
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MMC init failed when boot with upper SD slot
while succesful with lower slot.
This patch will fix it.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Accoring to board identification table, the ADC data
register value range between "0xB9E79F - 0xC00000"
indicates 21.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Removed low voltage (1.8V) from supported voltage ranges.
Changed SD2_CMD pad setting to enable SD2 r/w in uboot.
Loaded env from booted device instead of SD1 always.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Use ROM plug-in feature to init DDR and re-config PLL1 to
800Mhz due to ROM set it to 799Mhz. Plug-in has the following benifit
from ROM team comments,
1. DCD size limitation issue, plugin can be the size of OCRAM
free space region which is 72KB.
2. Safe environment to re-configure PLL1 (without impacting SDRAM)
as the plugin runs from OCRAM. This could get around the issue
of some boards running with ARM @ 192MHz due to the incorrect
GPIO configuration for Low Power Boot.
3. Ability to have one bootloader binary for both LPDDR1 & LPDDR2 platforms.
Signed-off-by: Jason Liu <r64343@freescale.com>
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Fix the build break for MX51 BBG board
Signed-off-by: Jason Liu <r64343@freescale.com>
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Add initial support for MX50
-Support mddr200Mhz, lpddr2266Mhz ARM2 board,
-Support boot from SD/MMC,
-Support boot from SPI-NOR,
-Support FEC, UART,
-Support SD/MMC/SPI command within UBOOT
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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CSPI: make spi_get_cfg platform specific
move the spi_get_cfg out of the cspi/ecspi driver
Signed-off-by:Jason Liu <r64343@freescale.com>
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