summaryrefslogtreecommitdiff
path: root/board/freescale
Commit message (Collapse)AuthorAgeLines
* ColdFire: Fix M5329EVB and M5373EVB nand issueTsiChung Liew2008-11-03-43/+31
| | | | | | | | | | | Fix compilation issue caused by a few mismatches. Provide proper nand chip select enable/disable in nand_hwcontrol() rather than in board_nand_init() just enable once. Remove redundant local nand driver functions - nand_read_byte(), nand_write_byte() and nand_dev_ready() to use common nand driver. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Add MCF5301x CPU and M53017EVB supportTsiChung Liew2008-11-03-0/+306
| | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Add SBF support for M52277EVBTsiChung Liew2008-11-03-5/+161
| | | | | | Add serial boot support Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Use CFI driver for M5272C3TsiChung Liew2008-11-03-379/+1
| | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Remove platforms mii.c fileTsiChung Liew2008-11-03-3430/+11
| | | | | | | | | | | Will use mcfmii.c driver in drivers/net rather than keep creating new mii.c for each future platform. Remove EB+MCF-EV123, cobra5272, idmr, M5235EVB, M5271EVB, M5272C3, M5275EVB, M5282EVB, M5329EVB, M5373EVB, M54451EVB, M54455EVB, M547xEVB, and M548xEVB's mii.c Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Remove linker fileTsiChung Liew2008-11-03-287/+0
| | | | | | | | Each different build for M54455EVB and M5235EVB will create a u-boot.lds linker file. It is redundant to keep the u-boot.lds Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* NAND: Add NAND support for MPC8536DS boardJason Jin2008-10-31-0/+6
| | | | | | | | | | This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file. It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image. Singed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc86xxWolfgang Denk2008-10-30-25/+0
|\
| * 86xx: remove the second DDR LAW setting for mpc8641hpcnDave Liu2008-10-30-3/+0
| | | | | | | | | | | | | | | | The DDR1 LAW will precedence the DDR2 LAW, so remove the second DDR LAW. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
| * 86xx: remove the unused ddr_enable_ecc in the board fileDave Liu2008-10-30-22/+0
| | | | | | | | | | | | | | | | | | The DDR controller of 86xx processors have the ECC data init feature, and the new DDR code is using the feature, we don't need the way with DMA to init memory again. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
* | NAND: Add support for MPC8572DS boardHaiying Wang2008-10-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines 1M TLB&LAW size for NAND on MPC8572DS, assigns 0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file. It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image, to make room for the increased code size with NAND enabled. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-29-4/+4
|/ | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* 86xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-90/+41
| | | | | | | | | | | | Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-269/+135
| | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* mpc83xx: add support for switching between USB Host/Function for MPC837XEMDSAnton Vorontsov2008-10-21-4/+2
| | | | | | | | | | With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov2008-10-21-0/+44
| | | | | | | | | | | | | | | | | | | | | | | The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add SGMII riser module support for the MPC8378E-MDS boardsAnton Vorontsov2008-10-21-0/+123
| | | | | | | | | | This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix serdes setup for the MPC8378E boardsAnton Vorontsov2008-10-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | MPC837xE specs says that SerDes1 has: — Two lanes running x1 SGMII at 1.25 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. And for SerDes2: — Two lanes running x1 PCI Express at 2.5 Gbps; — One lane running x2 PCI Express at 2.5 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. The spec also explicitly states that PEX options are not valid for the SD1. Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX, which is wrong to do. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: mpc8360emds: rework LBC SDRAM setupAnton Vorontsov2008-10-21-12/+27
| | | | | | | | | | | | | | | | | | | Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions). This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory). With this patch we're able to: - Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 85xx: Fix compile warning in mpc8536ds.cKumar Gala2008-10-21-1/+0
| | | | | | | mpc8536ds.c: In function 'is_sata_supported': mpc8536ds.c:615: warning: unused variable 'devdisr' Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-8/+8
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Enabled the Freescale SGMII riser card on 8536DSJason Jin2008-10-18-0/+42
| | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* Enabled the Freescale SGMII riser card on 8572DSLiu Yu2008-10-18-0/+48
| | | | | | | This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* Make pixis_set_sgmii more general to support MPC85xx boards.Liu Yu2008-10-18-3/+19
| | | | | | | | | | | | The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* mpc8572 additional end-point modeEd Swarthout2008-10-18-2/+2
| | | | | | | | | | | mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0. Include host_agent == 0 decode for end-point determination. This is not needed for the ds reference board since pcie3 will be a host in order to connect to the uli chip. Include it here as a reference for other mpc8572 boards. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* pixis do not print long help if not configuredEd Swarthout2008-10-18-0/+4
| | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* Add DDR options setting on MPC8641HPCN boardHaiying Wang2008-10-18-36/+110
| | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-28/+94
| | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-11/+44
| | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xx: Improve flash remapping on MPC8572DS & MPC8536DSKumar Gala2008-10-18-14/+10
| | | | | | | | Changing the flash from cacheable to cache-inhibited was taking a significant amount of time due to the fact that we were iterating over the full 256M of flash. Instead we can just flush the L1 d-cache and invalidate the i-cache. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-1573/+1573
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Fix compiler warning in lib_ppc/board.cHeiko Schocher2008-10-15-1/+1
| | | | | | | Fix compiler warning introduced by commit 0f8cbc18 Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Do not init SATA when disabled on 8536DS.Jason Jin2008-10-14-0/+12
| | | | | | | | | | SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the driver still try to access the SATA registers, the cpu will hangup. This patch try to fix this by reading the serdes status before the SATA initialize. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl_diu: fix alignment error that caused malloc corruptionNikita V. Youshchenko2008-10-14-3/+3
| | | | | | | | | | | | | | | | | | | When aligning malloc()ed screen_base, invalid offset was added. This not only caused misaligned result (which did not cause hardware misbehaviour), but - worse - caused screen_base + smem_len to be out of malloc()ed space, which in turn caused breakage of futher malloc()/free() operation. This patch fixes screen_base alignment. Also this patch makes memset() that cleans framebuffer to be executed on first initialization of diu, not only on re-initialization. It looks correct to clean the framebuffer instead of displaying random garbage; I believe that was disabled only because that memset caused breakage of malloc/free described above - which no longer happens with the fix described above. Signed-off-by: Nikita V. Youshchenko <yoush@debian.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-12-1/+1
|\
| * FSL: Fix get_cpu_board_revision() return value.Rafal Czubak2008-10-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | get_cpu_board_revision() returned board revision based on information stored in global static struct eeprom. It should instead use one from local struct board_eeprom, to which the data is actually read from EEPROM. The bug led to system hang after printing L1 cache information on U-Boot startup. The problem was observed on MPC8555CDS system and possibly affects other Freescale MPC85xx boards using CFG_I2C_EEPROM_CCID. The change has been successfully tested on MPC8555CDS system. Signed-off-by: Rafal Czubak <rcz@semihalf.com>
* | mpc83xx: spd_sdram: fix ddr sdram base address assignment bugAnton Vorontsov2008-09-24-6/+6
|/ | | | | | | | | | | The spd_dram code shifts the base address, then masks 20 bits, but forgets to shift the base address back. Fix this by just masking the base address correctly. Found this bug while trying to relocate a DDR memory at the base != 0. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-10/+10
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-3/+3
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename environment.c in env_embedded.c to reflect is functionalityJean-Christophe PLAGNIOL-VILLARD2008-09-10-21/+21
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Update Freescale 85xx boards to sys_eeprom.cTimur Tabi2008-09-09-61/+0
| | | | | | | | | The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID format, and so it obsoletes board/freescale/common/cds_eeprom.c. Freescale 86xx boards already use sys_eeprom.c, so this patch migrates the remaining Freescale 85xx boards to use it as well. cds_eeprom.c is deleted. Signed-off-by: Timur Tabi <timur@freescale.com>
* Moved initialization of EEPRO100 Ethernet controller to board_eth_init()Ben Warren2008-09-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards: db64360 db64460 katmai taihu taishan yucca cpc45 cpu87 eXalion elppc debris kvme080 mpc8315erdb integratorap ixdp425 oxc pm826 pm828 pm854 pm856 ppmc7xx sc3 sc520_spunk sorcery tqm8272 tqm85xx utx8245 Removed initialization of the driver from net/eth.c Also, wrapped contents of pci_eth_init() by CONFIG_PCI. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Moved initialization of TSI108 Ethernet controller to board_eth_init()Ben Warren2008-09-02-0/+10
| | | | | | | | | Affected boards: mpc7448hpc2 Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Moved initialization of RTL8139 Ethernet controller to board_eth_init()Ben Warren2008-09-02-4/+12
| | | | | | | | | | | | | Affected boards: hidden_dragon MPC8544DS MPC8610HPCN R2DPLUS TB0229 Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Introduce netdev.h header file and remove externsBen Warren2008-09-02-6/+2
| | | | | | | This addresses all drivers whose initializers have already been moved to board_eth_init()/cpu_eth_init(). Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Add pixis_set_sgmii commandAndy Fleming2008-09-02-0/+55
| | | | | | | | | | | | | | | | | | The 8544DS and 8572DS platforms support an optional SGMII riser card to expose ethernet over an SGMII interface. Once the card is in, it is also necessary to configure the board such that it uses the card, rather than the on-board ethernet ports. This can either be done by flipping dip switches on the motherboard, or by modifying registers in the pixis. Either way requires a reboot. This adds a command to allow users to choose which ports are routed through the SGMII card, and which through the onboard ports. It also allows users to revert to the current switch settings. This code does not work on the 8572, as the PIXIS is different. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Add SGMII support for the 8544 DSAndy Fleming2008-09-02-0/+39
| | | | | | | | | The 8544 DS has an optional SGMII Riser card, which uses different PHY addresses. Check if we are in SGMII mode, and invoke the SGMII Riser setup code if so. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Add support for Freescale SGMII Riser CardAndy Fleming2008-09-02-0/+42
| | | | | | | | | | | The 8544DS and 8572DS systems have an optional SGMII riser card which exposes new ethernet ports which are connected to the eTSECs via an SGMII interface. The SGMII PHYs for this board are offset from the standard PHY addresses, so this code modifies the passed in tsec_info structure to use the SGMII PHYs on the card, instead. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* ColdFire: Multiple fixes for MCF5445x platformsTsiChung Liew2008-08-28-6/+9
| | | | | | | | | | Add FEC pin set and mii reset in __mii_init(). Change legacy flash vendor from 2 to AMD LEGACY (0xFFF0), change cfi_offset to 0, and change CFG_FLASH_CFI to CONFIG_FLASH_CFI_LEGACY. Correct M54451EVB and M54455EVB env settings in configuration file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-08-28-34/+2711
|\
generated by cgit v1.1 at 2024-12-30 20:34:24 +0000