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* Prepare v2010.03-rc1v2010.03-rc1Wolfgang Denk2010-03-12-1/+0
| | | | | | Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* MX51: removed warnings for the mx51evkStefano Babic2010-03-07-10/+1
| | | | | | | | | | | The patch removes warnings at compile time and provides some cleanup code: - Removed comment on NAND (not yet supported) from lowlevel_init.S - Removed NFMS bit definition from imx-regs.h The bit is only related to MX.25/35 and can lead to confusion - Moved is_soc_rev() to soc specific code (removed from mx51evk.c) Signed-off-by: Stefano Babic <sbabic@denx.de>
* Add initial support for Freescale mx51evk boardStefano Babic2010-03-07-0/+649
| | | | | | | | The patch adds initial support for the Freescale mx51evk board. Network (FEC) and SD controller (fsl_esdhc) are supported. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2010-02-03-1/+2
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| * 83xx, uec: split enet_interface in two variablesHeiko Schocher2010-01-31-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | There's no sensible reason to unite speed and interface type into one variable. So split this variable enet_interface into two vars: enet_interface_type, which hold the interface type and speed. Also: add the possibility for switching between 10 and 100 MBit interfaces on the fly, when running in FAST_ETH mode. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Nand boot: Add nand boot support for MPC8569mds boardLiu Yu2010-01-27-0/+20
|/ | | | | | This patch add nand boot support for MPC8569mds board. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* ppc/85xx: Add PIB/ATM support for MPC8569mdsLiu Yu2010-01-25-1/+8
| | | | | Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-19/+19
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-01-12-1/+58
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| * mpc83xx: Add NAND boot support for MPC8315E-RDB boardsAnton Vorontsov2010-01-07-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core support for NAND booting is there already, so this patch is pretty straightforward. There is one trick though: top level Makefile expects nand_spl to be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code from mpc8313erdb boards, and so to not duplicate the code we just symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> o silence make during ln echo o update documentation o and avoid: $ ./MAKEALL MPC8315ERDB_NAND Configuring for MPC8315ERDB board... sdram.o: In function `fixed_sdram': /home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay' by renaming udelay -> __udelay in the spirit of commit 3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog support". Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc85xx: Add 4-bits eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2010-01-05-0/+14
| | | | | | | | | | | | | | | | | | Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 0" document, which describes all eSDHC pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Map boot page guarded for MP bootKumar Gala2010-01-05-3/+3
| | | | | | | | | | | | | | We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Make flash TLB entry determined at runtime on FSL boardsKumar Gala2010-01-05-4/+4
| | | | | | | | | | | | | | Rather than hard coding which TLB entry the FLASH is mapped with we can use find_tlb_idx to determine the entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on P2020 DSKumar Gala2010-01-05-7/+5
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on P1/P2 RDBKumar Gala2010-01-05-6/+4
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Move to using fsl_setup_hose on MPC8572 DSKumar Gala2010-01-05-8/+6
| | | | | | | | | | | | | | | | We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/86xx: Clean up MPC8610 HPCD PCI setup codeKumar Gala2010-01-05-137/+62
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8548 CDS PCI setup codeKumar Gala2010-01-05-93/+48
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8568 MDS PCI setup codeKumar Gala2010-01-05-92/+45
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8569 MDS PCI setup codeKumar Gala2010-01-05-60/+26
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8544 DS PCI setup codeKumar Gala2010-01-05-179/+70
| | | | | | | | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Clean up MPC8536 DS PCI setup codeMingkai Hu2010-01-05-191/+66
|/ | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 5xxx, fdt: move fdt_fixup_memory() to cpu.c fileHeiko Schocher2009-12-08-1/+0
| | | | | | | | u-boot updates, before starting Linux, the memory node in the DTS. As this is a "standard" feature, move this functionality to the cpu.c file for mpc5xxx and mpc512x processors. Signed-off-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' into nextWolfgang Denk2009-12-05-13/+0
|\ | | | | | | | | | | | | | | Conflicts: board/esd/plu405/plu405.c drivers/rtc/ftrtc010.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * mpc8260: move FDT memory node fixup into common CPU code.Marcel Ziswiler2009-11-22-13/+0
| | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com> Tested-by: Heiko Schocher <hs@denx.de>
* | Generic udelay() with watchdog supportIngo van Lil2009-12-05-1/+1
|/ | | | | | | | | | | | | According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
* 86xx: Remove redundant code in initdramBecky Bruce2009-11-04-10/+0
| | | | | | | | The same code exists both inside an #ifdef and outside of it. Remove the extra code for all the 86xx boards. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"Kumar Gala2009-11-04-8/+8
| | | | | | | | | | | This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc. There isn't any need to modify the API for fsl_pci_init_port to pass the status of host/agent(end-point) status. We can determine that internally to fsl_pci_init_port. Revert the patch that makes the API change. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Configure QE USB for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+36
| | | | | | | | Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Configure QE UART for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-21/+78
| | | | | | | | | | | | To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node. Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+6
| | | | | | | | SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+1
| | | | | | | | This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add eLBC NAND support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-19/+11
| | | | | | | | Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-1/+118
| | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-8/+8
| | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data ratePoonam Aggrwal2009-10-27-2/+2
| | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.Poonam Aggrwal2009-10-27-8/+8
| | | | | | | The data being modified was in NOR flash which caused the crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/P1_P2_RDB: On-chip BootROM supportDipen Dudhat2009-10-16-0/+12
| | | | | | | | | On Chip BootROM support for P1 and P2 series RDB platforms. This patch is derived from latest On Chip BootROM support on MPC8536DS Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/P1_P2_RDB: NAND Boot SupportDipen Dudhat2009-10-16-0/+17
| | | | | | | | | NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from NAND Boot support on MPC8536DS. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-10/+0
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| * ppc: Remove pci config table pointer relocation fixupsPeter Tyser2009-10-03-7/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | mpc512x: fix fixed_sdram() init code.Wolfgang Denk2009-10-08-6/+6
|/ | | | | | | | | | Commit 054197ba and later fixes used an array to initialize some of the MDDRC parameters; however, the use of an array turned out to be a bad idea as it was not possible to correlate structure entries to array indices in readable and reliable way. Now we use a struct instead, which makes this self-explanatory. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-09-30-0/+30
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| * On-chip ROM boot: MPC8536DS supportMingkai Hu2009-09-30-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address. The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again. This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * NAND boot: MPC8536DS supportMingkai Hu2009-09-30-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc83xx: mpc8360emds: Add QE USB device tree fixupsAnton Vorontsov2009-09-25-0/+12
| | | | | | | | | | | | | | | | With this patch we can change QE USB mode without need to hand-edit the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUsAnton Vorontsov2009-09-25-6/+50
| | | | | | | | | | | | | | | | | | This patch fixes various ethernet issues with gigabit links handling in U-Boot. The workarounds originally implemented by Kim Phillips for Linux kernel. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: mpc8360emds: Don't use LBC SDRAM when DDR is availableAnton Vorontsov2009-09-25-1/+4
|/ | | | | | | | | | | | | | | Since commit 5c2ff323a94e27e481f70c44838d43fcd844dd46 ("mpc8360emds: rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux. Though, it appears that QE Ethernet in Gigabit mode can't transmit large packets when it tries to work with a data in LBC SDRAM (memtest didn't discover any issues, is LBC SDRAM just too slow?). With this patch we can still use the board without DDR memory, but if DDR is available, we don't use LBC SDRAM. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]Wolfgang Denk2009-09-25-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
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