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* mpc85xx: Configure QE USB for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+36
| | | | | | | | Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Configure QE UART for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-21/+78
| | | | | | | | | | | | To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node. Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+6
| | | | | | | | SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+1
| | | | | | | | This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add eLBC NAND support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-19/+11
| | | | | | | | Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-1/+118
| | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-8/+8
| | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data ratePoonam Aggrwal2009-10-27-2/+2
| | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.Poonam Aggrwal2009-10-27-8/+8
| | | | | | | The data being modified was in NOR flash which caused the crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/P1_P2_RDB: On-chip BootROM supportDipen Dudhat2009-10-16-0/+12
| | | | | | | | | On Chip BootROM support for P1 and P2 series RDB platforms. This patch is derived from latest On Chip BootROM support on MPC8536DS Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/P1_P2_RDB: NAND Boot SupportDipen Dudhat2009-10-16-0/+17
| | | | | | | | | NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from NAND Boot support on MPC8536DS. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-10/+0
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| * ppc: Remove pci config table pointer relocation fixupsPeter Tyser2009-10-03-7/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | mpc512x: fix fixed_sdram() init code.Wolfgang Denk2009-10-08-6/+6
|/ | | | | | | | | | Commit 054197ba and later fixes used an array to initialize some of the MDDRC parameters; however, the use of an array turned out to be a bad idea as it was not possible to correlate structure entries to array indices in readable and reliable way. Now we use a struct instead, which makes this self-explanatory. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-09-30-0/+30
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| * On-chip ROM boot: MPC8536DS supportMingkai Hu2009-09-30-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address. The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again. This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * NAND boot: MPC8536DS supportMingkai Hu2009-09-30-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc83xx: mpc8360emds: Add QE USB device tree fixupsAnton Vorontsov2009-09-25-0/+12
| | | | | | | | | | | | | | | | With this patch we can change QE USB mode without need to hand-edit the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUsAnton Vorontsov2009-09-25-6/+50
| | | | | | | | | | | | | | | | | | This patch fixes various ethernet issues with gigabit links handling in U-Boot. The workarounds originally implemented by Kim Phillips for Linux kernel. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: mpc8360emds: Don't use LBC SDRAM when DDR is availableAnton Vorontsov2009-09-25-1/+4
|/ | | | | | | | | | | | | | | Since commit 5c2ff323a94e27e481f70c44838d43fcd844dd46 ("mpc8360emds: rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux. Though, it appears that QE Ethernet in Gigabit mode can't transmit large packets when it tries to work with a data in LBC SDRAM (memtest didn't discover any issues, is LBC SDRAM just too slow?). With this patch we can still use the board without DDR memory, but if DDR is available, we don't use LBC SDRAM. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]Wolfgang Denk2009-09-25-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add Elpida Memory Configuration to mpc5121ads BoardsMartha M Stan2009-09-25-2/+97
| | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor coding style cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc512x: Streamlined fixed_sdram() init sequence.Martha M Stan2009-09-25-1/+1
| | | | | | | | | | | | | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc8610hpcd: Use common 86xx fdt fixup codePeter Tyser2009-09-24-13/+1
| | | | | | | | Using the common 86xx fdt fixups removes some board-specific code and should make the mpc8610hpcd easier to maintain in the long run. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: 32bit DDR changes for P1020/P1011Poonam Aggrwal2009-09-24-5/+24
| | | | | | | | | | | | | The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up use of LAWAR definesKumar Gala2009-09-24-16/+16
| | | | | | | | | On 85xx platforms we shouldn't be using any LAWAR_* defines but using the LAW_* ones provided by fsl-law.h. Rename any such uses and limit the LAWAR_ to the 83xx platform as the only user so we will get compile errors in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up mpc8572DS PCI setup codeKumar Gala2009-09-24-157/+73
| | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up p2020ds PCI setup codeKumar Gala2009-09-24-117/+33
| | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up p1_p2_rdb PCI setupKumar Gala2009-09-24-20/+22
| | | | | | | | General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NAND boot: change NAND loader's relocate SP to CONFIG paramMingkai Hu2009-09-15-1/+1
| | | | | | | | | | So that we can set the NAND loader's relocate stack pointer to the value other than the relocate address + 0x10000. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link addressKumar Gala2009-09-09-0/+8
| | | | | | | | | | Some board ports place TEXT_BASE at a location that would cause the RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link. By default we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't explicitly set it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2009-09-08-57/+44
| | | | | | | | | | | Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-5/+0
| | | | | | | | The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: sys_eeprom: Fix 'may be used uninitialized' warningAnton Vorontsov2009-09-08-1/+2
| | | | | | | | The warning is bogus, so silence it by initializing the 'ret' variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: simplify the "mac id" command, improve boot-time informational messageTimur Tabi2009-08-28-32/+49
| | | | | | | | | | | | | | | | | | | | | | | | | The "mac id" command took a 4-character parameter as the identifier string. However, for any given board, only one kind of identifier is acceptable, so it makes no sense to ask the user to type it in. Instead, if the user enters "mac id", the identifier (and also the version, if it's NXID) will automatically be set to the correct value. Improve the message that is displayed when EEPROM is read during boot. It now displays "EEPROM:" and then either an error message or the EEPROM identifier if successful. If the identifier in EEPROM is valid, then always reject a bad CRC, even if the CRC field has not been initialized. Don't force the MAC address count to MAX_NUM_PORTS or less. Forcing the value to be changed resulting in an in-memory copy that does not match what's in hardware, even though the user did not request that change. Finally, always update the CRC value in the in-memory copy after any field is changed, so that the CRC is always correct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added PCIe support for P1 P2 RDBPoonam Aggrwal2009-08-28-1/+119
| | | | | | | Call fsl_pci_init_port() to initialize all the PCIe ports on the board. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Init pci ethernet cards if we enable any on MPC8572DSKumar Gala2009-08-28-1/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Move to a common linker scriptKumar Gala2009-08-28-1722/+0
| | | | | | | | There are really no differences between all the 85xx linker scripts so we can just move to a single common one. Board code is still able to override the common one if need be. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for P2020RDB boardPoonam Aggrwal2009-08-28-0/+809
| | | | | | | | | | | | | The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 86xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala2009-08-28-6/+0
| | | | | | | | | | | | For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 However these are all captured in the config.h and thus redudant. Also moved common 86xx flags into cpu/mpc86xx/config.mk. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala2009-08-28-43/+0
| | | | | | | | | | | | | For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 However these are all captured in the config.h and thus redudant. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Cleanup whitespace in mpc8536ds.cKumar Gala2009-08-28-11/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-73/+0
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-59/+24
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Convert CS8900 Ethernet driver to CONFIG_NET_MULTI APIBen Warren2009-08-25-0/+12
| | | | | | | | | | | | | | | All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900 - changed CS8900_BASE to CONFIG_CS8900_BASE - changed CS8900_BUS?? to CONFIG_CS8900_BUS?? - cleaned up line lengths - modified VCMA9 command function that accesses the device - removed MAC address initialization from lib_arm/board.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'next' of git://git.denx.de/u-boot-coldfireWolfgang Denk2009-08-04-3/+311
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| * ColdFire: Add M5208EVB and MCF520x CPU supportTsiChung Liew2009-07-14-0/+305
| | | | | | | | Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * ColdFire: Update for M54451EVBTsiChung Liew2009-07-14-3/+6
| | | | | | | | | | | | | | | | Update serial boot DRAM's Internal RAM, vector table and DRAM in start.S, serial flash's read status command over SPI and NOR flash. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* | Update Freescale copyrights to remove "All Rights Reserved"Kumar Gala2009-07-29-6/+6
| | | | | | | | | | | | "All Rights Reserved" conflicts with the GPL. Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
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