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* MLK-13407: mx6qarm2: mt128x64mx3 2: add init pre charge all commandAdrian Alonso2016-10-31-3/+10
| | | | | | | | | | | | | | | - Adjust ZQ delay for MMDC clock frequency at 400MHz - Precharge all commands per JEDEC The memory controller may optionally issue a Precharge-All command prior to the MRW Reset command, this is strongly recommended to ensure a robust DRAM initialization DDR Calibration script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/a72e010a1fd8c7fe0fda7bdc4d058c478e94c3da (Cherry-pick from commit id 03cc626df73d6c2bb36daf280b1cd43170c298a0) Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MA-8847-1 [Android_MX6SX_ARD] OTA: During online OTA based on NAND boot, ↵zhang sanshan2016-10-24-23/+26
| | | | | | | | | | | | | | can't install package.100% Add API to operate misc partition on nand device. Delete the API to operate SNVS register in uboot. Decide to the where to boot(fastboot or bootloader) according bootloader_message. Signed-off-by: zhang sanshan <b51434@freescale.com> changes in v2.1 compared with v2.0: 1 memalign a 3 pages size to hold misc info rather than 1M. Verified OTA and factory reset on sabreauto-6sx nand.
* MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividersAdrian Alonso2016-08-26-1/+1
| | | | | | | | Adjust ahb/axi clock root podf dividers to be divided by 1 to allow ahb/axi clock root to be 24Mhz when sourced from osc_clk. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13131: mx6qarm2: add fastboot and recovery supportAdrian Alonso2016-08-26-0/+33
| | | | | | Add fastboot and recovery mode support for mx6qarm Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13129: mx6qarm2: add lvds and hdmi supportAdrian Alonso2016-08-26-0/+214
| | | | | | | | Add video display support for mx6qarm2 target board Enable lvds and hdmi video displays only for mx6qarm2 lpddr2 pop target platform Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output settingYe Li2016-06-06-1/+1
| | | | | | | | LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3 is actually 1.2V. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12815: mx6ul_14x14_evk: add new NAND config for i.MX6UL 14x14 EVK boardHan Xu2016-05-18-1/+3
| | | | | | | add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when NAND enabled due to pin conflict. Signed-off-by: Han Xu <han.xu@nxp.com>
* MLK-12800 imx: mx7dsabresd: support revCPeng Fan2016-05-16-4/+13
| | | | | | | Add revC board support. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1f0bb3940876c9b0be6f3c5fc320dde81ced4d97)
* MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLLYe Li2016-05-16-0/+10
| | | | | | | | | | | | | In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 7f00c72e17e4e440df62aa4945a619fdbc9cfd8f)
* MLK-12748-3 imx: adjust imx7d lpddr3 lpsr exit flowAnson Huang2016-05-09-1/+13
| | | | | | | | | | | | On i.MX7D lpddr3, retention mode exit flow should restore more registers to make sure the ddr controller and ddr phy settings restored properly, otherwise, some of the boards can NOT pass memtester after retention mode exited. For LPSR mode, ddr resume flow is same as retention mode, just adjust it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-2 imx: remove IOMUXC GPR setting for i.mx7d retention modeAnson Huang2016-05-09-3/+3
| | | | | | | | i.MX7D TO1.2 removes the DDR PADs retention mode setting in IOMUXC GPR, it is same as TO1.0, so only apply the IOMUXC GPR setting for TO1.1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-1 imx: adjust i.mx7d standby voltage settingAnson Huang2016-05-09-16/+16
| | | | | | | i.MX7D VDD_ARM/SOC standby voltage should be 0.95V, adding 25mV margin, so set it to 0.975V; Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12629-2: i.MX6QP: update pluginPeng Fan2016-05-04-0/+12
| | | | | | | For i.MX6QP, the QoS settings is different from others. Align with DCD. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 8a7d61d0731725c6f79488e0089b0b5bd35d028a)
* MLK-12735 mx6qpsabresd: Update DDR script to version 1.14Ye Li2016-04-29-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR script file: arik_r2_sdb_ddr3_528_1.14.inc Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1 Update: setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 setmem /32 0x021b48c0 = 0x24914452 setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1 Test: Passed stress memtester on one board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2Anson Huang2016-04-27-59/+59
| | | | | | | i.MX7D TO1.2 uses same DDR script as TO1.0, TO1.1 uses dedicated DDR script. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12694 mx6ullarm2: Remove the CD detection of SD2Ye Li2016-04-22-3/+1
| | | | | | | | | Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause SD2 access problem even the card is inserted. Hard code the CD result to 1 to assume the card is always on. The SD driver will return other errors if the card does not exist. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12687 mx6ullarm2: Clean up macro usage for pins conflict devicesYe Li2016-04-21-8/+8
| | | | | | | | | | | | | | 1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which conflicts with QSPIA and NAND, that we have to disable them at same time. 2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which conflicts with SD2 and NAND, that we have to disable them at same time. 3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK 4. Enable QSPI support for default SD boot case. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12690 imx: mx6ull: fix build error for pluginPeng Fan2016-04-21-1/+1
| | | | | | | | Fix build error for Plugin "Can't stat board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin: Bad file descriptor" Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12677 mx6ullarm2: Update DDR script to version 2.1Ye Li2016-04-20-5/+6
| | | | | | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.inc Changes: Change ZQ_OFFSET to the default value:00 setmem /32 0x021B0890 = 0x00400000 Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11 setmem /32 0x020E0288 = 0x000C0030 Change duty cycle fine tune cell for SDCLK and SDQS setmem /32 0x021B08C0 = 0x00944009 Test: One mx6ull ARM2 board passed memtest. Signed-off-by: Ye Li <ye.li@nxp.com>
* MA-7633-1 [Android-SD-EMMC] enable BCB partition in androidzhang sanshan2016-04-14-1/+6
| | | | | | | | 1 Add some APIs to operate BCB/command. 2 Add action to check the command of BCB. It can cover the case that power down when do factory-reset\ota in recovery mode. Signed-off-by: zhang sanshan <b51434@freescale.com>
* MLK-12616-11 imx: mx6ull: add mx6ull arm2 board supportPeng Fan2016-04-12-0/+1221
| | | | | | | | | | | | Support mx6ull ddr3 arm2 board. DDR script version 1.1. Passed memtester on 3 boards. Take mx6ul 14x14 ddr3 arm2 as reference. Note: LCD/NAND/ECSPI not tested, need hardware rework. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12563: imx: mx6ul evk: fix LCD_nPWREN settingPeng Fan2016-03-15-1/+1
| | | | | | | Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3. If LCD_nPWREN is high, output is 2.4V which is not correct. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12551: imx6ul evk: fix 74LV OE usagePeng Fan2016-03-15-7/+1
| | | | | | | | | | | Fix 74LV OE gpio index. pinmux is correct, but gpio index is wrong, so gpio output will not have effect, since we use wrong GPIO5_IO18, but not correct GPIO5_IO8. And at the end of the initialization of 74lv init, should keep OE voltage level at LOW, but not high. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12492-1 mx6: fix type style problems introduced by patch MLK-12483Ye Li2016-03-04-17/+12
| | | | | | | Some type style problems found by review-commits for previous patch MLK-12483, fix them in this patch and re-check. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12483-5 mx6ul: Enable module fuse check EVK board and DDR3 ARM2 boardYe Li2016-03-04-2/+44
| | | | | | | Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for module fuse check. And modify board level codes for SD, FEC and EIM. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12442: imx: mx6qarm2: lpddr2 set dram 2 channel fixed modeAdrian Alonso2016-03-04-2/+11
| | | | | | | | | | | | | Setup MMDC in two channel fixed mode Initialize dram banks for two channel fixed mode DRAM bank = 0x00000000 -> start = 0x10000000 -> size = 0x20000000 DRAM bank = 0x00000001 -> start = 0x80000000 -> size = 0x20000000 Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-12371-2: imx: mx7dsabresd: fix POR reset failed after DDR enter retentionRobin Gong2016-03-04-0/+12
| | | | | | Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR retention mode before uboot boot, so add this in DCD and plugin code. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
* MLK-12371-1: imx: mx7d_12x12_lpddr3_arm2: fix POR reset failed after DDR ↵Robin Gong2016-03-04-2/+17
| | | | | | | | | | enter retention Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR retention mode before uboot boot, so add this in DCD and plugin code. Meanwhile correct the HW_ANADIG_SNVS_MISC_CTRL setting to avoid touching other bits. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
* MLK-12393: imx: mx6qamr2: update lpddr2 dcd programming aid settingsAdrian Alonso2016-03-04-5/+5
| | | | | | | | | | | | | | | Adjust optimal valid clock cycles for 400Mhz operation Adjust valid clock cycles before self-refresh exit tCKSRX Adjust valid clock cycles after self-refresh entry tCKSRE Set MMDC1_MPZQHWCCTRL upper 16 bits to default reset value DDR calibration script http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69 Test result: Stress test passed. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-12346 imx: mx7d: switch to use DRAM_PLL, but not DRAM_ALT_CLK_ROOTPeng Fan2016-03-04-24/+79
| | | | | | | To simplify kernel clock management, we switch to use DRAM_PLL for DRAM controller and DDR PHY, but not use DRAM_ALT_CLK_ROOT. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12329-1 imx7d: Update DDR script for TO1.1Ye Li2016-03-04-24/+998
| | | | | | | | | | | | | | | | | | | | On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated. When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards), DDR data corruption occured, not able to decrease CKE delay, so we have to add extra delay on all other signals to balance it. DDR script needs to be fine-tuned according to this hardware change. For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from 533Mhz to 400Mhz. Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name Test: Overnight tests passed on all changed boards. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12261 MX6DQ{P}/DL:SABRESD Fix bmode eMMC failureYe Li2016-03-04-1/+1
| | | | | | | | | | The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card. Fixed the value to correct one. The issue was fixed in 2014.04 u-boot, but that patch seems missed during porting to 2015.04. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-11811: imx: mx6qarm2: add new board revision supportAdrian Alonso2016-03-04-0/+294
| | | | | | | | | | | | Add mx6qarm2 new board revision support using mx6q pop SoC Enable DRAM support for imx6q PoP SoC with populated LPDDR2 MT42L128M64D2 DDR calibration script http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/e5c6184940486bcbc28978d60ad3cd996c205a08 Test result: Stress test passed. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* MLK-12034 imx: mx7dsabresd: Add RevB board supportYe.Li2016-03-04-41/+148
| | | | | | | | | | | | | Since i.MX7D SDB revB board has some HW changes, we have modify the BSP file to support new pinmux. 1. OTG2 PWR pin is changed to GPIO1_IO07. 2. A enet2_en pin is added for isolating enet2 signals with EPDC, we also add support for enet2. 3. pin6 of 74LV output is changed for CSI PWDN. Set output to high to power down it. This patch also tries to get the board id and apply changes according with it. Since current RevB board does not burn GP1 fuse for board id, we have to check the TO rev instead even it is not very exact. Will update this if any new way implemented. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-12017 imx: mx6ulevk: Update DDR script for new DDR MT41K256M16TW-107Ye.Li2016-03-04-0/+183
| | | | | | | | | | | | | | | | | | | Current Micron DDR MT41K256M16HA-125 on i.MX6UL will be EOL. Plan is i.MX6UL will use the new 20nm litho 4Gb DDR3L MT41K256M16TW-107. Update DDR script of mx6ul evk board for this new DDR, and use it as default. http://compass.freescale.net/livelink/livelink?func=ll&objId=234910940&objAction=browse&viewType=1 Test result: Stress test passed. Meanwhile add build targets below for old DDR support: mx6ul_14x14_evk_ddr_eol_android_defconfig mx6ul_14x14_evk_ddr_eol_brillo_defconfig mx6ul_14x14_evk_ddr_eol_defconfig mx6ul_14x14_evk_ddr_eol_qspi1_defconfig Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11995 ARM: imx7: add i.mx7d TO1.1 support for LPSR modeAnson Huang2016-03-04-6/+16
| | | | | | | | i.MX7D TO1.1 changes DDR retension mode control to IOMUXC_GPR, add support to this change for LPSR which needs to exit from DDR retension mode. Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
* MLK-11951 pfuze: Fix unsigned variable for less-than-zero comparisonYe.Li2016-03-04-1/+2
| | | | | | | | According to the Coverity result, a unsigned int variable is used fo less- than-zero comparison, the result is never true. Need to fix the variable type to signed int. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11892 imx: boards: fix variable typePeng Fan2016-03-04-7/+15
| | | | | | | ret should not use unsigned integer. Should use signed interger to compare against 0. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11825 imx: mx6dqp: update ddr script to 1.13Peng Fan2015-11-09-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI arik_r2_sdb_ddr3_528_1.13.inc is for sabresd 1.13<-1.12: Change log: 1. Remove 20c4080 1.12<-1.10 Change log: 1. NoC register DDRCONF change to 0 which is compatible for only CS0 is used on board 2. Change 2 values to compatible with our DDR aid script, these two registers doesn’t have any effect on current system tRPA = 0; //this bit only used in DDR2 mode tAOFPD/tAONPD=0x4; //These register only works when MDPDC. SLOW_PD = 1 which is 0 in script Test results: One mx6qp-sdb and one mx6qp-ard board and one mx6qp-ard board passed 60 hours memtester stress teset. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11795-02 imx: upate the pmic standby voltage for imx6qpBai Ping2015-10-30-28/+47
| | | | | | | | | | According to the latest datasheet(Rev. B, 07/2015), the VDD_SOC_IN standby voltage should be 1.05V and on i.MX6QP, we can use the PMIC 'APS' mode in standby. we add a 25mV margin to cover the IR drop and board tolerance, so the standby voltage of VDD_SOC_IN should be setting to 1.075V. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11795-01 imx: correct the vdd_arm regulator setting on imx6qpBai Ping2015-10-30-45/+101
| | | | | | | | | on i.MX6QP SDB board, the SW1A/B/C regulator is used by VDD_SOC_IN, the regulator of VDD_ARM_IN is SW2, the voltage setting for VDD_ARM_IN should be corresponding to SW2. So fix the regulator mismatch issue on i.MX6QP SDB board. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11799 imx: mx6qpsdb: update ddr script to 1.10Peng Fan2015-10-30-4/+4
| | | | | | | | | | | | | http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/963fbc75ef6d36e12819e81de23410749754e5ef http://compass.freescale.net/livelink/livelink?func=ll&objId=234709279&objAction=browse&viewType=1 Main change: (SDB board ddr density is different) 1. tRFC is different with density, tXS/tXPR refers tRFC Test Results: 2 MX6DP-SDB and 2 MX6QP-SDB boards passed overnight stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11753 imx: mx6dqp: update ddr script to v1.09Peng Fan2015-10-23-7/+17
| | | | | | | | | | | | | | | | | | | | | | ddr script update to 1.09: http://compass.freescale.net/livelink/livelink?func=ll&objId= 234694528&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.09.inc is for sabre-auto board. arik_r2_sdb_ddr3_528_1.09.inc is for sabre-sd board. Changelog: 1. Optimize DQS duty cycle setting 2. Optimize ZQ PU/PD value Test results: 2 ARD boards. 2 6QP-SDB boards. 1 6DP-SDB board. All passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit ba8dcef9d8e10e46130559ce6defe4411bd1d1a6)
* MLK-11675 ARM: imx: change the VDD_SOC normal voltage to 0.975VBai Ping2015-10-13-0/+37
| | | | | | | | | According to the latest datasheet(Rev. C Draft 1, 10/2015) of i.MX7D, change the VDD_SOC voltage to 0.95V in run mode, and add a 25mV margin to cover the IR drop and board tolerance. So setting VDD_SOC voltage to 0.975V. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11682 imx: mx6ul: Update DDR script of 14x14 EVK board to 1.2 revYe.Li2015-10-10-21/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | IC team releases new DDR script "EVK_IMX6UL_DDR3L_400MHz_16bit_V1.2.inc", update it to DCD and plugin for i.MX6UL 14x14 EVK board. Updated items: Removed: 0x020c4084 0x021B0858 Value changed: 0x020E027C 0x020E0280 0x021B0008 0x021B000C 0x021B0010 0x021B0018 0x021B08C0 The script versions of EVK board and Validation Board from the following link: http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj Action=browse&viewType=1 Test Results: Two boards passed overnight memtester stress test. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11662-2 imx: mx6ul: Modify the MMDC automatic Power saving timerYe.Li2015-09-30-1/+1
| | | | | | | | The PST bit can't be set too small which will cause performance drop. Refer the commit for same issue on MX6UL 9x9 EVK, now fix it for 14x14 LPDDR2 ARM2 commit e1ca547d198dde94c4d8278c99499ec2d2008880 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11662-1 imx: mx6ul: Change 14x14 LPDDR2 ARM2 memory size to 256MBYe.Li2015-09-30-1/+1
| | | | | | | The actual memory size is 256MB not 512MB, otherwise it has a wrap problem in memory and will cause memtester failed. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11622 imx6dqp-sabresd: update ddr script to v1.08Robby Cai2015-09-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable bank interleave feature to improve the performance downloaded from http://compass.freescale.net/livelink/livelink?func=ll&objId=234609508&objAction=browse&viewType=1 Before: $ /opt/fsl-samples/g2d/g2d_test Width 1920, Height 1088, Format RGBA, Bpp 32 ---------------- g2d blit performance ---------------- g2d blit time 15566us, 64fps, 134Mpixel/s ........ g2d blending time 20672us, 48fps, 101Mpixel/s ........ g2d blend-dim time 13616us, 73fps, 153Mpixel/s ........ ---------------- g2d clear performance ---------------- g2d clear time 8433us, 118fps, 247Mpixel/s ........ ---------------- g2d rotation performance ---------------- 90 rotation time 15366us, 65fps, 135Mpixel/s ........ 180 rotation time 15374us, 65fps, 135Mpixel/s ........ 270 rotation time 15373us, 65fps, 135Mpixel/s ........ g2d flip-h time 15373us, 65fps, 135Mpixel/s ........ g2d flip-v time 15372us, 65fps, 135Mpixel/s ........ ... After: $ /opt/fsl-samples/g2d/g2d_test Width 1920, Height 1088, Format RGBA, Bpp 32 ---------------- g2d blit performance ---------------- g2d blit time 2810us, 355fps, 743Mpixel/s ........ g2d blending time 4025us, 248fps, 518Mpixel/s ........ g2d blend-dim time 2740us, 364fps, 762Mpixel/s ........ ---------------- g2d clear performance ---------------- g2d clear time 1846us, 541fps, 1131Mpixel/s ........ ---------------- g2d rotation performance ---------------- 90 rotation time 5234us, 191fps, 399Mpixel/s ........ 180 rotation time 3176us, 314fps, 657Mpixel/s ........ 270 rotation time 5248us, 190fps, 398Mpixel/s ........ g2d flip-h time 2765us, 361fps, 755Mpixel/s ........ g2d flip-v time 3179us, 314fps, 657Mpixel/s ........ ... Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-11551 imx: mx6qpsabresd: Update DDR initialization in pluginYe.Li2015-09-16-0/+180
| | | | | | The DDR initialization in plugin needs to update conformably with DCD. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11549 imx: imx6ul: enlarge MMDC_MAPSR.PST to 16Anson Huang2015-09-15-1/+1
| | | | | | | | | MMDC auto power saving timer can NOT be too small, as enter/exit auto self-refresh mode too frequently may introduce too many latency for MMDC access, set it to 0x10, same as previous value on i.MX6. Signed-off-by: Anson Huang <b20788@freescale.com>
generated by cgit v1.1 at 2025-04-23 17:16:19 +0000