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* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-02-10-28/+172
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| * mx53loco: Fix boot hang during reboot stress testFabio Estevam2015-02-10-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently by running the following test: => setenv bootcmd reset => save => reset , we observe a hang after approximately 20-30 minutes of stress reboot test. Investigation of this issue revealed that when a single DDR chip select is used, the hang does not happen. It only happens when the two chip selects are active. MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence": "The controller must keep the memory lines quiet (except for CK) for the ZQ calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256 for other ZQCL and 64 for ZQCS)." According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL: "Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines. Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)" So make sure to activate one chip select at time (CS0 first and then CS1 later), so that the required JEDEC delay is respected for each chip select. With this change applied the board has gone through three days of reboot stress test without any hang. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6qsabreauto: Change to use common GPMI IO clock functionYe.Li2015-02-10-23/+2
| | | | | | | | | | | | | | | | Since a clock function setup_gpmi_io_clk is implemented for GPMI IO clock settings, change to use this common function in GPMI setup. Signed-off-by: Ye.Li <B37916@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx:mx6sxsabresd board spl supportPeng Fan2015-01-22-0/+169
| | | | | | | | | | | | Add board level spl support for mx6sxsabresd board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * mx6sxsabresd: Remove unneeded board_late_init()Fabio Estevam2015-01-19-5/+0
| | | | | | | | | | | | | | | | Since commit 1f98e31bc0b2c37a ("imx: mx6sxsabresd: Use the pfuze common init function") board_late_init() became empty, so we can safely remove this unneeded function. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | fsl/ls1021qds: Add deep sleep supporttang yuantian2015-01-24-0/+43
| | | | | | | | | | | | | | | | Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
* | arm: ls102xa: Add LPUART support for LS1021ATWR boardAlison Wang2015-01-23-0/+1
| | | | | | | | | | | | | | | | This patch adds LPUART support for LS1021ATWR board. For ls1021atwr_nor_lpuart_defconfig, LPUART is used as the console. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | arm: ls102xa: Add LPUART support for LS1021AQDS boardAlison Wang2015-01-23-0/+1
| | | | | | | | | | | | | | | | This patch adds LPUART support for LS1021AQDS board. For ls1021aqds_nor_lpuart_defconfig, LPUART is used as the console. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | arm: ls102xa: Update snoop settings for CCI-400Alison Wang2015-01-23-17/+29
| | | | | | | | | | | | | | | | | | | | | | CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. These CCI-400 operations are moved to board_early_init_f() to be initialized earlier. For S4 slave interface, issuing of snoop requests and DVM message requests are enabled. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ls102xa: dcu: Add platform support for DCU on LS1021AQDS boardXiubo Li2015-01-23-0/+99
| | | | | | | | | | | | | | | | | | | | This patch adds the CH7301 HDMI options and the common configuration for DCU on LS1021AQDS board. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Cc: Jason Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as defaultAlison Wang2015-01-23-1/+34
| | | | | | | | | | | | | | | | | | | | This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will be used via hwconfig. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc: mpc85xx: remove P2020DS board supportMasahiro Yamada2015-01-23-536/+0
| | | | | | | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | powerpc: mpc85xx: remove P2020COME board supportMasahiro Yamada2015-01-23-439/+0
| | | | | | | | | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Ira W. Snyder <iws@ovro.caltech.edu>
* | powerpc: mpc85xx: remove P1_P2_RDB boardsMasahiro Yamada2015-01-23-1108/+0
| | | | | | | | | | | | | | | | These boards are still non-generic boards: P1011RDB, P1022RDB, P2010RDB, P2020RDB Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* | powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS supportMasahiro Yamada2015-01-23-1259/+1
| | | | | | | | | | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Dave Liu <daveliu@freescale.com> Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-01-22-45/+315
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| * | board/T1040rdb: Add VSC9953 support for T1040rdb boardCodrin Ciubotariu2015-01-21-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | This patch configures and initializes the L2 switch on T1040rdb board. The external L2 switch ports may be connected to PHYs only over QSGMII, for T1040rdb. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
| * | board/T1040qds: Add VSC9953 support for T1040qds boardCodrin Ciubotariu2015-01-21-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | This patch configures and initializes the L2 switch on T1040QDS board. The L2 switch ports must be initialized according to the SerDes protocols. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
| * | board/T104xrdb: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYsCodrin Ciubotariu2015-01-21-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's T1040qds board may be configured to have up to 5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports, 2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2), connected to other two ports from an intergrated VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link ports have no PHYs attatched, so they don't have a corresponding MDIO. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/T1040qds: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYsCodrin Ciubotariu2015-01-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's T1040qds board may be configured to have up to 5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports, 2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2), connected to other two ports from an intergrated VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link ports have no PHYs attatched, so they don't have a corresponding MDIO. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/T1040qds: Fix lane-to-slot mapping for SerDes protocol 0x89Codrin Ciubotariu2015-01-21-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t1040qds: convert deep sleep to generic board interfacetang yuantian2015-01-16-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t102xqds: convert deep sleep to generic board interfacetang yuantian2015-01-16-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t1024rdb: Add support for T1024RDB-PBShengzhou Liu2015-01-16-4/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY. rcw_0x095 is used for 10G XFI + 3x PCIex1 rcw_0x135 is used for 2.5G SGMII + 2x PCIex1 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t102xrdb: convert deep sleep to generic board interfacetang yuantian2015-01-16-12/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Besides, added SPI/SD/NAND boot deep sleep support. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc: SECURE BOOT- Add secure boot target for T1042RDBgaurav rana2015-01-16-0/+1
| | | | | | | | | | | | | | | | | | | | | Secure boot target is added for T1042RDB platform. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t4240rdb: Add alternate SerDes 2 protocol to align with RCWChunhe Lan2015-01-16-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes 2 protocol 56 is not valid any longer due to the new RCW; protocol 55 is used instead, so add SerDes 2 protocol 55 to align with RCW. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for P5040DSgaurav rana2015-01-16-0/+1
| | | | | | | | | | | | | | | | | | | | | Secure boot target is added for P5040DS platform. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/c29xpcie: Add secure boot supportPo Liu2015-01-16-0/+2
| |/ | | | | | | | | | | | | | | Add NOR and SPI flash secure boot target for C29XPCIE board. Signed-off-by: Po Liu <Po.Liu@freescale.com> Signed-off-by: Mingkai.Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | MAINTAINERS: add me as the maintainer of mpc837xerdbSinan Akman2015-01-20-2/+2
| | | | | | | | | | Signed-off-by: Sinan Akman <sinan@writeme.com> Cc: Tom Rini <trini@ti.com>
* | imx: ls102xa: Remove reference to gdataSimon Glass2015-01-20-6/+0
|/ | | | | | | | The global_data pointer (gd) has already been set before board_init_f() is called. We should not assign it again. We should also not use gdata since it is going away. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: 74xx_7xx: remove 74xx_7xx cpu supportMasahiro Yamada2015-01-16-1864/+0
| | | | | | | | | | | | | All the 74xx_7xx boards are still non-generic boards: P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2 Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Nye Liu <nyet@zumanetworks.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
* mpc8260: remove MPC8266ADS board supportMasahiro Yamada2015-01-05-1101/+0
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rune Torgersen <runet@innovsys.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-0/+41
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| * imx:mx6slevk add spi nor boot supportPeng Fan2014-12-31-0/+1
| | | | | | | | | | | | | | Add spi nor boot support for mx6slevk board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * imx:mx6sxsabresd add qspi supportPeng Fan2014-12-31-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the pad setting and enable qspi clock to support qspi flashes access. Add QSPI related macro in configuration header file. Note: mx6sxsabresd Revb board, 32M flash is used, but in header file, CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT initialization qspi_set_lut function uses 32BIT addr, however CONFIG_SPI_FLASH_BAR and 24BIT addr should be used to access bigger than 16MB size flash, and BRRD/BRWR should also be supported. Future patches will fix this. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | mx6slevk: Remove get_board_rev()Fabio Estevam2014-12-30-5/+0
| | | | | | | | | | | | | | | | | | | | get_board_rev() just returns the cpu revision, which does not make it really useful for distinguishing between revisions of the board. Let's get rid of get_board_rev() as it is not being used with its correct meaning. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx51evk: Fix MX51EVK_USB_CLK_EN_B definitionFabio Estevam2014-12-19-1/+1
| | | | | | | | | | | | As per the mx51evk schematics MX51EVK_USB_CLK_EN_B is GPIO2_1, not GPIO2_2. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx:mx6qarm2 add board level support for usbPeng Fan2014-12-19-0/+42
| | | | | | | | | | | | Add pinmux settings and implement board_ehci_hcd_init Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | imx:mx6sabresd add board level support for usbPeng Fan2014-12-19-0/+68
|/ | | | | | Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* mpc85xx/t104xrdb: convert deep sleep to generic board interfaceTang Yuantian2014-12-15-29/+33
| | | | | | | | A new interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-1/+98
|\ | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * imx:mx6sxsabresd add board level support for usbPeng Fan2014-11-14-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6sxsabresd board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to make host port work in HOST mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
| * imx:mx6slevk add board level support for usbPeng Fan2014-11-14-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to let host port work in host mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-16/+756
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| * | ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-11-0/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls1021aqds: add hwconfig setting to do pin muxYao Yuan2014-12-11-3/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale LS1021AQDS share some pins, so Add the hwconfig option that allows the user to choose which the function he wants. The main pin mux IP is: eSDHC, SAI, IIC2, RGMII, CAN, SAI. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-23 02:37:25 +0000