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* Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2012-09-30-1876/+503
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| * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2012-09-25-1635/+161
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| | * powerpc/mpc85xx/p1_p2_rdb: add all LAWs during SPLScott Wood2012-08-23-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LAW init is skipped in the SPL payload because it's assumed that the SPL has taken care of it -- so make sure the SPL loads all the LAWs as is done on other boards. This bug was introduced by: commit 4589728e214958a4e6e011a081a68d360c49d7a5 Author: Kumar Gala <galak@kernel.crashing.org> Date: Fri Nov 11 08:14:53 2011 -0600 powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND Size grew a bit so nand-spl didn't fit in 4k, reduce done by removing LAW entries not needed during SPL phase. Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-1556/+0
| | | | | | | | | | | | | | | | | | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: get rid of enum board_slots in P4080 MDIO driverTimur Tabi2012-08-23-40/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and so on. This is pointless, so remove it. Also move the lane_to_slot[] array to the top of the file so that it can be used by other functions. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: introduce function serdes_device_from_fm_port()Timur Tabi2012-08-23-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to figure out which SerDes lane a given Fman port is connected to, we need a function that maps the fm_port namespace to the srds_prtcl namespace. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * mpc85xx: use LCRR_DBYP define instead of raw constantPaul Gortmaker2012-08-23-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the raw value of 0x80000000 directly in the code can lead to "count the zeros" bugs like that fixed in commit 718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC") Change all existing raw values to use the symbolic value of LCRR_DBYP instead. Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit)Matthew McClintock2012-08-23-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was an extra 0 in front of the value we were using to mask, remove it to improve the code. Also fix the value written to ddr_sdram_cfg to set the bus width properly to 16 bits Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/CoreNet: add tool to support pbl image build.Shaohui Xie2012-08-23-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides a tool to build boot Image for PBL(Pre boot loader) which is used on Freescale CoreNet SoCs, PBL can be used to load some instructions and/or data for pre-initialization. The default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/corenet_ds: Slave module for boot from PCIELiu Gang2012-08-23-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Slave's ucode and ENV can be stored in master's memory space, then slave can fetch them through PCIE interface. For the corenet platform, ucode is for Fman. NOTE: Because the slave can not erase, write master's NOR flash by PCIE interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Put the slave's ucode and ENV into it's own memory space. 4. Normally boot from local NOR flash. 5. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the slave module, need to finish these processes: 1. Set the boot location to one PCIE interface by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID of one PCIE for the boot. 4. Set a specific TLB entry in order to fetch ucode and ENV from master. 5. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 6. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. In addition, the processes are very similar between boot from SRIO and boot from PCIE. Some configurations like the address spaces can be set to the same. So the module of boot from PCIE was added based on the existing module of boot from SRIO, and the following changes were needed: 1. Updated the README.srio-boot-corenet to add descriptions about boot from PCIE, and change the name to README.srio-pcie-boot-corenet. 2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to "xxxx_SRIO_PCIE_BOOT", and the image builded with "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and from PCIE. 3. Updated other macros and documents if needed to add information about boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macroLiu Gang2012-08-23-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-91/+42
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| * | | ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455Alison Wang2012-09-20-56/+66
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF547x and MCF548xAlison Wang2012-09-20-32/+36
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF523xAlison Wang2012-09-20-19/+24
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301xAlison Wang2012-09-20-55/+61
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF52x2Alison Wang2012-09-20-65/+81
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF5227xAlison Wang2012-09-20-14/+16
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | mpc8308rdb: add support for eSDHC MMC controllerIra W. Snyder2012-09-18-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the onboard eSDHC MMC controller. The hardware on the MPC8308RDB has the following errata: - ESDHC111: manual asynchronous CMD12 is broken - DMA is broken (PIO works) Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> [added include fsl_esdhc header to prevent implicit declarations of fsl_esdhc_mmc_init() and fdt_fixup_esdhc()] Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc8308rdb: add support for Spansion SPI flash on header J8Ira W. Snyder2012-09-18-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI pins are routed to header J8 for testing SPI functionality. A Spansion flash has been wired up and tested on this header. This patch breaks support for the second TSEC interface, since the GPIO pin used as a chip select is pinmuxed with some of the TSEC pins. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | | mx28evk: Remove fecmxc_mii_postcall()Fabio Estevam2012-09-24-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fecmxc_mii_postcall() is specific to the KSZ9021 PHY on m28evk and should not be used on mx28evk, which has LAN8270 instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* | | | mx51evk: Add CONFIG_REVISION_TAGBenoît Thébaudeau2012-09-23-0/+8
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | mx35pdk: README: Remove NAND referencesFabio Estevam2012-09-17-76/+2
| | | | | | | | | | | | | | | | | | Booting from NAND is currently not supported, so remove its references. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | MX35: mx35pdk: add support for MMCStefano Babic2012-09-10-0/+25
| | | | | | | | | | | | | | | | | | | | | Add support for SD card and change the default environment due to increased u-boot size. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | mx6qsabrelite:Use IMX_GPIO_NR MacroAshok Kumar Reddy2012-09-10-12/+12
| | | | | | | | | | | | Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
* | | mx28evk: Convert to mxs_adjust_memory_params()Fabio Estevam2012-09-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent conversion from mx28_adjust_memory_params to mxs_adjust_memory_params missed to update mx28evk, which caused the board not to boot. Apply the conversion so that the board can boot again. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* | | MX28: mx28evk: Align SSP clock speedOtavio Salvador2012-09-04-2/+2
|/ / | | | | | | | | | | | | | | Align the SSP clock speed with oscilator to achieve higher transfer stability. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* | fsl_esdhc: Remove cache snooping for i.MXBenoît Thébaudeau2012-09-01-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so disable it globally for this architecture. This avoids setting no_snoop for all i.MX boards, and it prevents setting a reserved bit of a reserved register if fsl_esdhc_mmc_init() is used on i.MX, like in arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init(). Since no_snoop was only used on i.MX, get rid of it BTW. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com>
* | mx5:Use IMX_GPIO_NR macroAshok Kumar Reddy2012-09-01-20/+20
| | | | | | | | Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
* | mx6qarm2:Use IMX_GPIO_NR macroAshok Kumar Reddy2012-09-01-2/+2
| | | | | | | | | | | | Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | mxs: Rename 'mx28_dram_init' to 'mxs_dram_init'Otavio Salvador2012-09-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM initialization, after SPL has complete, is exactly the same for all mxs SoCs so we should name it accordinly. The following boards has been changed: * apx4devkit * m28evk * mx28evk * sc_sps_1 Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
* | mx53ard: Use IMX_GPIO_NR macroFabio Estevam2012-09-01-1/+1
| | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx51evk: Use IMX_GPIO_NR macroFabio Estevam2012-09-01-3/+3
| | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx53loco: Use IMX_GPIO_NR macroFabio Estevam2012-09-01-1/+1
| | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | MX: Set a common gpio.h for all i.MXStefano Babic2012-09-01-14/+14
| | | | | | | | | | | | | | | | | | Each i.MX has its own gpio.h, defining the same structure. The internal GPIO controller has the same layout (at least for the register used by u-boot) and can be shared. Signed-off-by: Stefano Babic <sbabic@denx.de> Tested-by: Matt Sealey <matt@genesi-usa.com>
* | mx53evk: add boot_mode supportTroy Kisky2012-09-01-0/+13
| | | | | | | | | | | | | | This allows a watchdog reset to start the ROM's usb/serial downloader, or boot from an sdcard. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* | mx6qsabrelite: add boot_mode supportTroy Kisky2012-09-01-0/+14
| | | | | | | | | | | | | | This allows a watchdog reset to start the ROM's usb downloader, or boot from an sdcard. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* | iomux: move IOMUX_GPR13_xxx definesTroy Kisky2012-09-01-0/+1
| | | | | | | | | | | | | | Move mx6 specific defines to arch-mx6 directory. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx35: Fix typo on EDIOBenoît Thébaudeau2012-09-01-1/+1
| | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | MX28: Move the u-boot.bd info CPUDIR/SOCDIRMarek Vasut2012-09-01-14/+0
| | | | | | | | | | | | | | | | This gets us rid of duplication of the same file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx51evk: do not overwrite the consoleFabio Estevam2012-09-01-1/+9
| | | | | | | | | | | | | | On this board, the console is always set to the serial line. Do not allow to overwrite it when video is enabled. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | MX5: mx53loco: do not overwrite the consoleStefano Babic2012-09-01-6/+6
| | | | | | | | | | | | | | | | | | On this board, the console is always set to the serial line. Do not allow to overwrite it when video is enabled. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mxs: Reowork SPL to use 'mxs' prefix for methodsOtavio Salvador2012-09-01-1/+1
| | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | mxs: prefix register structs with 'mxs' prefixOtavio Salvador2012-09-01-2/+2
|/ | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* powerpc/sgmii: To support PHY link state auto detect in SGMII modeHongtao Jia2012-08-08-8/+49
| | | | | | | | | | | | | | | PHYs on SGMII riser card are used in SGMII mode with different external IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type under ethernet node should be updated. Otherwise the PHY interrupt can not be handled therefor PHY link state change can not be auto detected. For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed but it's still be kept to guarantee the sgmii mode could work with old device tree. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p2041: configure the CPLD lane_mux according to RCWShaohui Xie2012-08-08-0/+39
| | | | | | | | | | | | | | | | | | | Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg is 0xc, CPLD supports SATA by default, we should re-configure the lane muxing according to RCW, which indicates what SerDes protocol it is running. Default lane muxing map is as below: Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg; Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg; Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2 and bit 3 respectively. Default value of these bits for lane muxing is '1', we should set or clear these bits accoring to RCW. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p1022ds: fix DIU/LBC switching with NAND enabledTimur Tabi2012-08-08-8/+74
| | | | | | | | | | | In order for indirect mode on the PIXIS to work properly, both chip selects need to be set to GPCM mode, otherwise writes to the chip select base addresses will not actually post to the local bus -- they'll go to the NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM mode before switching to indirect mode. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p1022ds: add support for SPI and SD bootMatthew McClintock2012-08-08-0/+18
| | | | | | | | | | | | | | | | | | Add TLB mappings, board target options, and configuration items need for SPI/SD boot. Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them. Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mx6qsabrelite: add i2c multi-bus supportTroy Kisky2012-07-31-4/+46
| | | | | | | This includes bus recovery support. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Jason Liu <r64343@freescale.com>
* i.mx: iomux-v3.h: move to imx-common include directoryTroy Kisky2012-07-31-3/+3
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
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