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* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-1168/+1525
|\ | | | | | | | | | | Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h
| * imx: mx35pdk: Fix MUX2_CTR GPIOBenoît Thébaudeau2013-05-06-1/+1
| | | | | | | | | | | | | | MUX2_CTR is on GPIO1[5], not GPIO2[5], and it needs to be set high in order to connect the FEC. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * mx23evk: Do not set voltage selection bit for SSP padsFabio Estevam2013-05-06-1/+1
| | | | | | | | | | | | mx23 SSP pad registers do not contain voltage selection bit, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * imx: mx53smd: Convert to iomux-v3Benoît Thébaudeau2013-05-05-104/+48
| | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: mx53loco: Convert to iomux-v3Benoît Thébaudeau2013-05-05-223/+113
| | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: mx53evk: Convert to iomux-v3Benoît Thébaudeau2013-05-05-206/+83
| | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: mx53ard: Convert to iomux-v3Benoît Thébaudeau2013-05-05-186/+141
| | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: mx51evk: Convert to iomux-v3Benoît Thébaudeau2013-05-05-239/+131
| | | | | | | | | | | | | | There is no change of behavior, except for older silicon revisions for which support is removed. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: mx35pdk: Convert to iomux-v3Benoît Thébaudeau2013-05-05-99/+74
| | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: mx35pdk: Fix WDOG_RST iomux functionBenoît Thébaudeau2013-05-05-1/+1
| | | | | | | | | | | | | | The signal connected from this pin to the PMIC is WDOG_B, i.e. ALT0 mode, not ALT1 (which even corresponds to nothing). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: mx25pdk: Fix GPIO assignmentsBenoît Thébaudeau2013-05-05-2/+2
| | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: mx25pdk: Convert to iomux-v3Benoît Thébaudeau2013-05-05-53/+75
| | | | | | | | | | | | | | There is no change of behavior, even if some pad control values could probably be simplified. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * mx23evk: Fix DDR pin iomux settingsFabio Estevam2013-05-05-1/+1
| | | | | | | | | | | | | | Change MUX_CONFIG_EMI to use the same drive strength as the bootlets code from Freescale, which results in much better stability. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * imx: iomux-v3: Include PKE and PUE to pad control pull definitionsBenoît Thébaudeau2013-04-28-66/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PUE requires PKE to mean something, as do pull values with PUE, so do not compell users to explicitly use PKE and PUE everywhere. This is also what is done on Linux and what has already been done for i.MX51. By the way, remove some unused pad control definitions. There is no change of behavior. Note that SPI_PAD_CTRL was defined by several boards with a pull value, but without PKE or PUE, which means that no pull was actually enabled in the pad. This might be a bug in those boards, but this patch does not change the behavior, so it just removes the meaningless pull value from those definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: Homogenize and fix fuse register definitionsBenoît Thébaudeau2013-04-28-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * mx53ard: Move register masks into imx-regs.hFabio Estevam2013-04-25-2/+0
| | | | | | | | | | | | | | imx-regs.h is more appropriate location for containing register masks. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * mx6qsabresd: Return status when initializing MMCOtavio Salvador2013-04-25-6/+7
| | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR registerFabio Estevam2013-04-25-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz. CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c from the mainline kernel. mx6q_4x_mt41j128.cfg is also used by mx6qsabresd, and it is safe to use it for this board as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * imx: Add titanium board support (i.MX6 based)Stefan Roese2013-04-22-0/+560
| | | | | | | | | | | | | | | | | | | | Titanium is a i.MX6 based board from ProjectionDesign / Barco. This patch adds support for this board with the newly introduced NAND support for i.MX6. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sl: Add initial support for mx6slevk boardFabio Estevam2013-04-22-0/+248
| | | | | | | | | | | | | | | | | | | | mx6slevk board is a development board from Freescale based on the mx6 solo-lite processor. For details about mx6slevk, please refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX6SLEVK&parentCode=i.MX6SL&fpsp=1 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PCXu Jiucheng2013-05-02-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When P1021RDB-PC reboot system, the board will hung at uboot DDR configuration. For P1021RDB-PC DDR reset pin is multiplex with QE, so uboot will reserve this pin for QE and skip DDR reset. Other platforms without QE will do this reset. This patch adds a slight code to reset DDR chip by QE CE_PB8 pin for NAND and NOR FLASH boot. For booting from SPI FALSH and SD card, it seems possible to use the rom on chip to write to the GPIO pins before configuring the DDR. Signed-off-by: Xu Jiucheng <B37781@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/p1010rdb: Change flexcan compatible stringShengzhou Liu2013-05-02-1/+1
| | | | | | | | | | | | | | | | Change flexcan compatible string from "fsl,flexcan-v1.0" to "fsl,p1010-flexcan" to match the device tree. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | qoriq/p1_p2_rdb_pc: USB device-tree fixups for P1020Zhicheng Fan2013-05-02-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | Resolve P1020 second USB controller multiplexing with eLBC - mandatory to mention USB2 in hwconfig string to select it over eLBC, otherwise USB2 node is removed - works only for SPI and SD boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Zhicheng Fan <B32736@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/b4860qds: Add the tlb entries for SRIO interfacesLiu Gang2013-05-02-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the tlb entries based on the configuration of the SRIO interfaces. Every SRIO interface has 256M space: #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/p1022ds: Add support for NAND and NAND boot using SPLMatthew McClintock2013-05-02-6/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add defines needed to access NAND, remove second flash bank that is actually connected to NAND. Add nand booting support for P1022DS with hardcoded DDR config using SPL framework from 2011 Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | board/freescale/common/cds_pci_ft.c: Fix rotate wrong cells in interrupt-map ↵Jiang Bin2013-05-02-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | property For linux 3.x, the size of each item in interrupt-map property is 9 not 7. Don't use the static value and calculate the size with following cells: PCI #address-cells, PCI #interrupt-cells, PIC address, PIC #address-cells, PIC #interrupt-cells. Signed-off-by: Bin Jiang <bin.jiang@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | env_mmc: add support for redundant environmentMichael Heimpold2013-05-01-1/+1
|/ | | | | | | | This patch add support for storing the environment redundant on mmc devices. Substantially it re-uses the logic from the NAND implementation, that means using an incremental counter for marking newer data. Signed-off-by: Michael Heimpold <mhei@heimpold.de>
* ARM: Fix __bss_start and __bss_end in linker scriptsAlbert ARIBAUD2013-04-13-4/+10
| | | | | | | | | | | | | | Commit 3ebd1cbc introduced compiler-generated __bss_start and __bss_end__ and commit c23561e7 rewrote all __bss_end__ as __bss_end. Their merge caused silent and harmless but potentially bug-inducing clashes between compiler- and linker- generated __bss_end symbols. Make __bss_end and __bss_start compiler-only, and create __bss_base and __bss_limit for linker-only use. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* arm: Make all linker scripts compatible with per-symbol sectionsBenoît Thébaudeau2013-04-12-9/+9
| | | | | | | | Let all ARM linker scripts handle properly -ffunction-sections and -fdata-sections. This will be useful for future changes in order to create symbol-specific sections in common .S files. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* arm: Remove unused relocate_code() parametersBenoît Thébaudeau2013-04-12-1/+1
| | | | | | | | Commit e05e5de7fae5bec79617e113916dac6631251156 made the 2 1st parameters of ARM's relocate_code() useless since it moved the code handling them to crt0.S. So, drop these parameters. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* nand: mxc: Switch NAND SPL to generic SPLBenoît Thébaudeau2013-04-12-5/+11
| | | | | | | | | This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: mx53ard: Add support for NAND FlashBenoît Thébaudeau2013-04-12-0/+66
| | | | | | | | | | | Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard. eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this board, which satisfies the 30-ns NF R/W cycle requirement. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-16/+62
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| * i.MX6: mx6qsabrelite: README: don't pass chip-select to sf probe commandJavier Martinez Canillas2013-04-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | board/freescale/mx6qsabrelite/README explain a procedure to update the SPI-NOR on the SabreLite board without Freescale manufacturing tool but following this procedure leads to both "sf erase" and "sf write" failing on a mx6qsabrelite board: MX6QSABRELITE U-Boot > sf probe 1 MX6QSABRELITE U-Boot > sf erase 0 0x40000 SPI flash erase failed MX6QSABRELITE U-Boot > sf write 0x10800000 0 0x40000 SPI flash write failed This is because the chip-select 1 is wrong and the correct value is 0x7300. Since commit c1173bd0 ("sf command: allow default bus and chip selects") the chip-select and bus arguments for the sf probe command are optional so let's just remove it and use "sf probe" instead. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
| * mx6: Fix get_board_rev() for the mx6 solo caseFabio Estevam2013-04-03-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev() returns 0x62xxx, which is not a value understood by the VPU (Video Processing Unit) library in the kernel and causes the video playback to fail. The expected values for get_board_rev are: 0x63xxx: For mx6quad/dual 0x61xxx: For mx6dual-lite/solo So adjust get_board_rev() accordingly and make it as weak function, so that we do not need to define it in every mx6 board file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a boardAbbas Raza2013-04-03-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com> cc: stefano Babic <sbabic@denx.de> cc: Andy Fleming <afleming@gmail.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * mx6qsabrelite: README: No need to pass 'u-boot.imx'Fabio Estevam2013-04-03-1/+1
| | | | | | | | | | | | | | The u-boot.imx binary is generated by default, so no need to pass it in the 'make' line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6qsabre{sd,auto}: Add boot mode selectOtavio Salvador2013-04-03-0/+40
| | | | | | | | | | | | | | | | Adds support for 'bmode' command which let user to choose where to boot from; this allows U-Boot to load system from another storage without messing with jumpers. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * mx6qsabresd: Fix card detection for invalid card id caseOtavio Salvador2013-04-03-4/+10
| | | | | | | | | | | | | | This changes the code so in case an unkown value is passed it will return as invalid. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * mx6qsabresd: Document the mapping of USDHC[2-4]Otavio Salvador2013-04-03-0/+7
| | | | | | | | | | | | | | This documents the SD card identifier so it is easier for user to spot which card number will be used, if need. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-03-18-297/+307
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard being added to in mainline and enhanced in u-boot-arm/master with proper formatting. Conflicts: arch/arm/cpu/ixp/u-boot.lds arch/arm/cpu/u-boot.lds arch/arm/lib/Makefile board/actux1/u-boot.lds board/actux2/u-boot.lds board/actux3/u-boot.lds board/dvlhost/u-boot.lds board/freescale/mx31ads/u-boot.lds doc/README.scrapyard include/configs/tegra-common.h Build tested for all of ARM and run-time tested on am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-274/+278
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| | * mx6: Provide a structure for accessing HDMI registersFabio Estevam2013-03-07-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | Provide a structure for accessing HDMI registers, so that we can use proper read/write accessors. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * mx23evk: Adjust DRAM control register to use full 128MB of RAMOtavio Salvador2013-03-07-0/+10
| | | | | | | | | | | | | | | | | | | | | Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full 128MB of RAM. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * i.MX6: consolidate pad names for multi-CPU boardsEric Nelson2013-03-07-215/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename all i.MX6 pad declarations to MX6_PAD_x, so a board may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo (MX6DL) by including the proper header. Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd only support MX6Q, so they include mx6q_pins.h. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6: mx6qsabrelite: indent with tabsEric Nelson2013-03-07-53/+53
| | | | | | | | | | | | | | | | | | | | | This patch has no functional changes and simply replaces leading spaces with tabs. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2013-02-23-83/+2631
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| | * | imx: mx6q DDR3 init: Benefit from available CL = 7Benoît Thébaudeau2013-02-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it. In these conditions: tRCD(min) = 13.125 ns tRP(min) = 13.125 ns tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min) tRAS(min, DDR3-1333H) = 36 ns tRAS(min, DDR3-1600K) = 35 ns MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG0[3:0]. MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18]. MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG1[2:0]. MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[31:29]. MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[28:26]. MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded as 0x1A in the bit-field MMDC1_MDCFG1[25:21]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * | imx: mx6q DDR3 init: Fix MR0.PPDBenoît Thébaudeau2013-02-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * | imx: mx6q DDR3 init: Fix RST_to_CKEBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
generated by cgit v1.1 at 2024-12-19 02:04:19 +0000