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* fsl: Change fsl_phy_enet_if to phy_interface_tAndy Fleming2011-04-20-6/+11
| | | | | | | | | | | | The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum. This meant that drivers which used fsl_phy_enet_if to deal with PHY interfaces would have to convert between the two (or we would have to have them mirror each other, and deal with the ensuing maintenance headache). Instead, we switch all clients of fsl_phy_enet_if over to phy_interface_t, which should become the standard, anyway. Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Detlev Zundel <dzu@denx.de>
* tsec: Convert tsec to use PHY LibAndy Fleming2011-04-20-0/+68
| | | | | | | | | | | | | This converts tsec to use the new PHY Lib. All of the old PHY support is ripped out. The old MDIO driver is split off, and placed in fsl_mdio.c. The initialization is modified to initialize the MDIO driver as well. The powerpc config file is modified to configure PHYLIB if TSEC_ENET is configured. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
* powerpc/85xx: Add PBL boot from SPI flash support on P4080DSShaohui Xie2011-04-10-1/+11
| | | | | | | | | | | | | PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DSJiang Yutang2011-04-10-11/+45
| | | | | | | | | | | For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable eSDHC boot support on P2020 DSJerry Huang2011-04-04-1/+77
| | | | | | | | | | | We implement our own mmc_get_env_addr since the environment variables are written to just after the u-boot image on SDCard, so we must read the MBR to get the start address and code length of the u-boot image, then calculate the address of the env. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add 36-bit address map support to P1022DSJiang Yutang2011-04-04-0/+3
| | | | | Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDBPoonam Aggrwal2011-04-04-4/+8
| | | | | | | | Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDBPoonam Aggrwal2011-04-04-2/+2
| | | | | | | | | | | | Changed the following DDR timing parameters for 800Mt/s: tRRT BL/2+1 to BL/2 tWWT BL/2+1 to BL/2 tWRT BL/2+1 to BL/2 tRWT BL/2+1 to BL/2 REFINT 6500ns to 7800ns Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Removed P1/P2 RDB RevB supportPoonam Aggrwal2011-04-04-22/+7
| | | | | | | | RevB boards never really made it outside of Freescale and have been replaced with RevC & RevD which had various board bug fixes. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Read board switch settings on p1_p2_rdbPriyanka Jain2011-04-04-0/+25
| | | | | | | | | | | | | | | | | | | | | PCA9557 is parallel I/O expansion device on I2C bus which stores various board switch settings like NOR Flash-Bank selection, SD Data width. On board: switch SW5[6] is to select width for eSDHC ON - 4-bit [Enable eSPI] OFF - 8-bit [Disable eSPI] switch SW4[8] is to select NOR Flash Bank for Booting OFF - Primary Bank ON - Secondary Bank Read board switch settings on p1_p2_rdb and configure corresponding eSDHC width. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdbPriyanka Jain2011-04-04-13/+15
| | | | | | | | | | | | | | | | | | Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: obsolete NXID v0 EEPROMs, automatically upgrade them to NXID v1Timur Tabi2011-04-04-10/+40
| | | | | | | | | | | | | | | | | | The NXID EEPROM format comes in two versions, v0 and v1. The only difference is in the number of MAC addresses that can be stored. NXID v0 supports eight addresses, and NXID v1 supports 23. Rather than allow a board to choose which version to support, NXID v0 is now considered deprecated. The EEPROM code is updated to support only NXID v1, but it can still read EEPROMs formatted with v0. In these cases, the EEPROM data is loaded and the CRC is verified, but the data is stored into a v1 data structure. If the EEPROM data is written back, it is written in v1 format. This allows existing v0-formatted EEPROMs to continue providing MAC addresses, but any changes to the data will force an upgrade to the v1 format, while retaining all data. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update fixed DDR3 timing table for P4080DSYork Sun2011-04-04-8/+8
| | | | | | | | | Most of time U-boot doesn't get an exact clock number. For example, clock 900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the table to align the desired clocks in the middle. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala2011-04-04-333/+0
| | | | | | | | | | | | | | Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala2011-04-04-84/+1
| | | | | | | | | | Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Remove config.mk for nand linker scriptKumar Gala2011-04-04-121/+0
| | | | | | | Move the include of mpc85xx/u-boot-nand.lds to utilize CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Move cpu specific lmb reserve to arch_lmb_reserveKumar Gala2011-04-04-57/+5
| | | | | | | | We've been utilizing board_lmb_reserve to reserve the boot page for MP systems. We can just move this into arch_lmb_reserve for 85xx & 86xx systems rather than duplicating in each board port. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add eSDHC support on P2020DSJerry Huang2011-04-04-0/+13
| | | | | | | | | | | We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9 respectively). We enable EXT2, FAT, and parition support for both MMC & USB configs. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>Kumar Gala2011-04-04-6/+0
| | | | | | | | | Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr initKumar Gala2011-04-04-35/+28
| | | | | | | | | | Rather than having #defines DATARATE_*_MHZ, lets just match what we do on the SPD code and convert the DDR frequency into MHZ and just compare with a constant. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* p1022ds: allow for board-specific ngPIXIS functionsTimur Tabi2011-04-04-18/+112
| | | | | | | | | | | | | | | | The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC SOCs. Although programming the ngPIXIS is mostly standard on all boards that have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in "indirect" mode whenever the video display (DIU) is active. To support indirect mode, and to make it easier to support other quirks on future reference boards, the low-level ngPIXIS functions are all marked as weak, so that board-specific code can override any of them. We take advantage of this feature on the P1022DS, so that we can properly reset the board when the DIU is active. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-03-27-23/+23
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| * rename _end to __bss_end__Po-Yu Chuang2011-03-27-23/+23
| | | | | | | | | | | | | | Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* | powerpc/85xx: Fix PCI memory map setup on P1_P2_RDBPrabhakar Kushwaha2011-03-24-2/+2
| | | | | | | | | | | | | | | | | | Update the PCIe address map to match standard FSL memory map. Additionally, fix the TLBs so the cover the PCIe address space properly so cards plugged in like an e1000 work correctly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8572ds: revise board specific timing for dual-rank DIMMsYork Sun2011-03-24-32/+78
|/ | | | | | | | Tested all possible values for clk_adjust and write_data_delay for dual rank UDIMM and RDIMM to revise the tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/corenet_ds: revise platform dependent parametersYork Sun2011-03-05-4/+4
| | | | | | | | This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* corenet_ds: pick the middle value for all tested timing parametersYork Sun2011-03-05-40/+18
| | | | | | | | | | | For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent. The best values should be picked up from the middle of all working combinations. This patch updates the table with confirmed values tested on Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s, 900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s, 1200MT/s, 1000MT/s. Signed-off-by: York Sun <yorksun@freescale.com>
* mx31pdk: Make the full boot log visibleFabio Estevam2011-02-21-1/+6
| | | | | | Use board_early_init_f so that the full boot log output can be displayed. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx31pdk: Use the new relocation schemeFabio Estevam2011-02-21-2/+8
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* fsl: update CRC after setting EEPROM identifierTimur Tabi2011-02-09-0/+1
| | | | | | | | | | The "mac id" command is used to initialize the EEPROM data to a specific format, but it was not updating the CRC. This didn't cause any real problems, because writing the data to the EEPROM will always update the CRC anyway, but it did result in a bogus CRC warning. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add support for Freescale's mx35pdk board.Stefano Babic2011-02-02-0/+810
| | | | | | | | | | | | | | | | | The patch adds suupport for the Freescale's mx35pdk board (known as well as mx35_3stack). The board boots from the NOR flash. Following devices are supported: - two ethernet devices (FEC and SMC911x on debug board) - I2C - PMIC (MC13892) via I2C interface - UART - NOR flash (64MB) - NAND flash (2GB) - basic access to mc9sdz60 registers via I2C interface Signed-off-by: Stefano Babic <sbabic@denx.de>
* MX51EVK: Use SWx macros in PMIC initMarek Vasut2011-02-02-3/+3
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* MX5:MX53: add initial support for MX53EVK boardLiu Hui-R643432011-02-02-0/+581
| | | | | | | Add initial support for MX53EVK board support. FEC, SD/MMC, UART, I2C, have been supported. Signed-off-by: Jason Liu <r64343@freescale.com>
* MX51EVK: UART does not print out the early informationLiu Hui-R643432011-02-02-3/+8
| | | | | | | | | | | | | | The early bootup information is not print out due to the UART pin iomux not set up correctly before board_init Add the board_early_init_f function and enable the CONFIG_BOARD_EARLY_INIT_F. Move the UART pin setting from board_init to board_early_init_f function. This patch also move the FEC pin iomux setup to the board_early_init_f. Signed-off-by: Jason Liu <r64343@freescale.com>
* ppc/85xx: Fix compile err when PCI disabled on P1_P2_RDBPrabhakar Kushwaha2011-01-19-2/+6
| | | | | | | | | u-boot cannot be compiled after disabling CONFIG_PCI. Place PCI related codes under #ifdef CONFIG_PCI Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* corenet_ds: Extend board specific parametersYork Sun2011-01-19-78/+81
| | | | | | | | | Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.hKumar Gala2011-01-19-92/+3
| | | | | | | | | | | Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr codeKumar Gala2011-01-14-16/+2
| | | | | | | | Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Convert MPC8641HPCN to use common SRIO init codeKumar Gala2011-01-14-4/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Convert MPC8569MDS to use common SRIO init codeKumar Gala2011-01-14-2/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Convert MPC8568MDS to use common SRIO init codeKumar Gala2011-01-14-2/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Convert MPC8548CDS to use common SRIO init codeKumar Gala2011-01-14-9/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor SRIO initialization into common codeKumar Gala2011-01-14-44/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-116/+2
| | | | | | | Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-64/+16
| | | | | | | | Remove duplicated code in MPC8610HPCD board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-62/+2
| | | | | | | | Remove duplicated code in P1_P2_RDB boards and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-41/+2
| | | | | | | | Remove duplicated code in MPC8569MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-39/+14
| | | | | | | | Remove duplicated code in MPC8568MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-41/+12
| | | | | | | | Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-53/+2
| | | | | | | | Remove duplicated code in MPC8641HPCN board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-25 13:42:14 +0000