| Commit message (Collapse) | Author | Age | Lines |
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Disable PFuze3000 low power mode during standby mode, otherwise,
if the power consumption exceed the threshold, PFuze will reboot.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Updated items:
memory set 0x307a0000 32 0x03040001 --> memory set 0x307a0000 32 0x01040001
This is just enable when LPDDR4 is enabled .
memory set 0x307a0064 32 0x0040005e --> memory set 0x307a0064 32 0x00400046
T_RFC_MIN this should be: RU(260ns*528Mhz)/2=69 (0x45)
memory set 0x307a00d0 32 0x00020001 --> memory set 0x307a00d0 32 0x00020083
PRE_CKE_X1024 be (500us*528Mhz/2)/1024 = 129, or 0x81
memory set 0x307a00d4 32 0x00010000 --> memory set 0x307a00d4 32 0x00690000
DRAM_RSTN_X1024 (200us*528Mhz)/1024=104, or 0x68
memory set 0x307a00e4 32 0x00090004 --> memory set 0x307a00e4 32 0x00100004
DEV_ZQINIT_X32 . Should be 16 clocks
memory set 0x307a0100 32 0x0908120a --> memory set 0x307a0100 32 0x09081109
T_FAW=(40ns*528Mhz)/2)=11
memory set 0x307a0104 32 0x0002020e --> memory set 0x307a0104 32 0x0007020d
tXPDLL=24ns*528Mhz=13clocks
File:
MX7D_EVK_DDR3_1GB_32bit.ds
Test result:
3 boards pass 2 days stress test.
Signed-off-by: Ye.Li <B37916@freescale.com>
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i.MX6UL-9x9-EVK board has PFUZE3000, so enable LDO
bypass support for this board.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This mx7d 19x19 lpddr2 arm2 board is based on 19x19 lpddr3 arm2 board
with DDR changed to 512M LPDDR2. We added DDR script for LPDDR2 and
a new u-boot build target: mx7d_19x19_lpddr2_arm2_config
LPDDR2 script source: lpddr2_0_1.ds
Signed-off-by: Ye.Li <B37916@freescale.com>
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The i.mx6ul 9x9 EVK shares the same base board with 6ul 14x14 EVK
with two main changes on CPU board:
1. Change to use pfuze 3000.
2. Use 256MB LPDDR2 memory.
This patch uses a macro CONFIG_6UL_9X9_LPDDR2 to distinguish the changes above,
basing on 14x14 EVK board level codes.
The new build target for the 9x9 EVK: mx6ul_9x9_evk_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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In LPSR mode, wdog will be reset when resume, need
to disable wdog powerdown timer to avoid system
reset after timeout setting of 16 seconds.
Signed-off-by: Anson Huang <b20788@freescale.com>
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For imx7d 12x12-lpddr3-arm2 board, when system enters LPSR
mode and waked up, ARM core will be reset and uboot needs to be
executed first, the LPSR register contains a resume entery,
if this entry is non-zero, then it means it is a resume from
LPSR mode, uboot plug in code needs to make DRAM exit from
retention mode then jump to the entry directly, otherwise,
it is a cold boot, normal boot process will be performed.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Since setup_waveform_file in different boards code have same implementation,
move setup_waveform_file to board common code. Also rename it to
board_setup_waveform_file
This patch also fix a bug when using flush_cache. We should pass
'waveform_buf' to flush_cache, but not a string named 'addr'.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Support draw image on E-ink screen.
1. The image format should be PGM-P5 raw data format.
2. The image should be named epdc_logo.pgm.
3. If no epdc_logo.pgm found in the first partition(FAT), will choose
to draw black border on the screen.
4. Default configuration is to draw image at pos (0,0). If 'splashpos'
env is set, will choose the pos from 'splashpos'.
5. The image size should not be bigger than screen total pixel size.
6. Implement board_setup_logo_file in board/freescale/common/epdc_setup.c
7. Introudce function prototype for board_setup_logo_file.
Note: i.MX7D EPDC supports advanced mode and standard mode. Since current
PXP in uboot for i.MX7D not ready, only support standard mode now.
advanced and standard mode needs waveform firmware's support.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Datasheet Rev-B defines standby voltage as 1V for i.MX7D, we add
25mV for board level IR drop.
Signed-off-by: Anson Huang <b20788@freescale.com>
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As the HDMI splash screen feature is not well supported,
we should not set it to be the default display. In case,
users leave the 'panel' uboot environment variable empty
and connect the board with a HDMI monitor, the HDMI detect
funtion will work and enable the HDMI splash screen. So,
this patch disables HDMI detect function so that users
may only explicitly set the 'panel' variable to be 'HDMI'
to use HDMI splash screen.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This pin is missed to change in patch:
"MLK-11230 imx6: USB: Modify OTG ID pin pad setting to pull up"
Should set it to pull down at default.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The SW1AB on PMIC is used for ARM_SOC_IN supply, set the standby voltage to
0.975V to save power when system is in DSM mode.
Signed-off-by: Bai Ping <b51503@freescale.com>
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To CD/VSELECT/RST, should use same pad settings with USDHC_PAD_CTRL,
because default NO_PAD_CTRL's settings is 100K Pull-Down. But, we need
pull-up for CD/VSELECT/RST.
Also some board provides external pull-down/up, we'd better use internal
pull-up for these pad settings.
To mx7d_12x12_lpddr3_arm2:
If no card plugged in, "mmc dev 1" will show "Card did not respond to
voltage select". After apply this patch, it will show "MMC: no card present".
To mx7dsabresd:
Alougth without this patch, if no card plugged in sd1, still correct msg
"MMC: no card present", anyway we'd better use pull-up.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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1. Replace the UDC driver with community's USB gadget d_dnl driver.
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Change the booti command to boota, due to the booti has been used for
ARM64 image boot.
5. Modify boota implementation to load ramdisk and fdt to their loading
addresses specified in boot.img header, while bootm won't do it for
android image.
6. Modify the android image HAB implementation. Authenticate the boot.img
on the "load_addr" for both SD and NAND.
7. Enable new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
8. Use community's way to combine cmdline in boot.img and u-boot environment,
not overwrite the cmdline in boot.img
Signed-off-by: Ye.Li <B37916@freescale.com>
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Update ddr script to version 1.07:
1. Change MDCCR from default value to 0x24912492,
it will improve DDR duty cycle
2. The MMDC reorder bypass option, which has better DRAM performance
URL:
http://compass.freescale.net/livelink/livelink?func=ll&objId=234335046&objAction=browse&viewType=1
Test Results:
3 boards passed 48 hours memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Set the ID pin pad to pull up not the pull down at default, otherwise
we can't enter the device mode, but always detect as host.
After this change we have to use portA cable to play as host,
and use portB cable for device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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1. Add weimnor boot defconfig
2. move CONFIG_FSL_USDHC and CONFIG_VIDEO to board header
3. Add CONFIG_SYS_FLASH_PROTECTION for mx6ul 14x14 lpddr2 arm2
4. correct CONFIG_SYS_FLASH_SECT_SIZE and CONFIG_SYS_MAX_FLASH_SECT
5. Add comments for setup_eimnor, since ENET2_RXER pin conflicts
with ENET2. Also eimnor support will disable SD1/SD2, need ENET
to boot kernel and nfs using enet. So setup_eimnor should be
invoked after setup_fec
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The current pad DSE for QSPI is 60ohm. Per hardware team measurement,
this setting cause too strong drive to clock and data signals. Need
to change the DSE to 120ohm for better signal quality.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Remove epdc qos settings from plugin.S, since set_epdc_qos does same thing.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add missed Kconfig files for mx7d_12x12_ddr3_arm2 board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add MX6UL LPDDR2 ARM2 board BSP codes, supported peripherals:
SD1, eMMC(USDHC2), USB OTG1, I2C, ENET2, PMIC.
Due to a board issue, the SD1 only supports 1 bit bus width.
Signed-off-by: Ye.Li <B37916@freescale.com>
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We should use board_spi_cs_gpio and remove the GPIO from
CONFIG_SF_DEFAULT_CS.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Abstracted the CSF size in imximage from a hardcoded value to a config
setting CONFIG_CSF_SIZE. This configuration is only enabled for secure
boot.
Increased the size of the CSF default allocation to 0x4000. This size
covers the event the worst case of 4906-bits keys.
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When using watchdog timeout in kernel, the reset does not output the
WDOG_B signal, so the power supply won't be reset. To solve the problem,
we enable it in u-boot.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Update the DDR script for i.MX7D 12x12 LPDDR3 ARM2 board and
i.MX7D 19x19 LPDDR3 ARM2 board to file "7D_lpddr3_0_3.ds5"
Updated items:
Changes DRAMTMG2 WR2RD from 7 to 8.
Compass link for this script:
http://compass.freescale.net/livelink/livelink?func=ll
&objid=233861153&objAction=browse&sort=name
Test results:
Passed overnight test on two MX7D 12x12 LPDDR3 ARM2 board
Passed overnight test on one MX7D 19x19 LPDDR3 ARM2 board
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since directory name changed, need to change it in imximage.cfg, or
we will get "Can't stat board/freescale/mx6ulevk/plugin.bin".
Since this commit 7331a4cc0853722b4c3addf1927a2797f39f5de2
missed to update ddr, here update the plugin code.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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updated DDR Script of 6UL EVK Board to avoid a calibration error
when using “DDR_Stress_Tester_V1.04.exe”.
Updated items:
[Modified] setmem /32 0x020E027C = 0x00000008
[Modified] setmem /32 0x020E0280 = 0x00000038
[Modified] setmem /32 0x021B080C = 0x00070007
[Added ] setmem /32 0x021B0858 = 0x00000F00
The script versions of EVK board and Validation Board from the following link:
http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj
Action=browse&viewType=1
Test Results:
Tested on two boards, both passed overnight memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since the flash blocks are locked at default , need to set
"CONFIG_SYS_FLASH_PROTECTION" to unlock them before write/erase.
The patch also add the pinmux for LBA (ADV) pin and set eimnor enabled at
default.
Signed-off-by: Ye.Li <B37916@freescale.com>
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1. There is conflict when building secure boot, because some common
codes for MPC are included by using same configuration. So modify the
makefile to get rid of them.
2. The 6UL arch config is missed in hab.h. Fix this issue by using
the CONFIG_ROM_UNIFIED_SECTIONS.
Signed-off-by: Ye.Li <B37916@freescale.com>
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i2c_pad_info3's i2c index should 2, but not 1. Correct it.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since there is another 9x9 package for mx6ul, modify the BSP names
of ddr3 arm2 board and evk board to add 14x14 package info.
Also modify the loaded dtb file to align with kernel.
After the change, the build target for mx6ul ddr3 arm2 board is:
mx6ul_14x14_ddr3_arm2_config
and the build target for mx6ul evk board is:
mx6ul_14x14_evk_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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On MX7D, boot rom can provide some boot information such as boot device,
arm freq, axi freq, etc. (see the structure below)
Offset Byte4 | Byte3 | Byte2 | Byte1
0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved
0x4 ARM core frequency(in Hz)
0x8 AXI bus frequency(in Hz)
0x0C DDR frequency(in Hz)
0x10 GPT1 input clock frequency(in Hz)
0x14 Reserved
0x18
0x1C
The boot information can be accessed by get the pointer at 0x1E8. This patch
changes the u-boot to use the new approach. When manufacture boot, the info
recorded is the actual SD port, not the failed device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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If no epdc pannel is plugged into mx6slevk board, no need to
do the elan init operation for each i2c init transfer which
will slow the i2c speed.
If epdc panned is plugged into mx6slevk board, all works as the
original patch: "b6ba68516b681a38025252bd0ef6a6ed3e8adfa0" -
"MLK-10215 Add elan init in i.MX6SL-EVK board"
This patch also fix a bug that setup_elan_pads should be called in
board_init, but not board_late_init where too late to setup_elan_pads.
And align pad property with linux kernel, value is 0x17000.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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* Add mx7d_19x19_lpddr3_arm2 target board supprt
* Enable i2c, spinor, usb, usdhc, qspi, enet, uart
* Build targets
mx7d_19x19_lpddr3_arm2_defconfig
mx7d_19x19_lpddr3_arm2_eimnor_defconfig
- Set EIMNOR settings for Intel Sibley Asynchronous mode
- Set flash sector size for 256kb (erase block size)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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This piece of code will never be compiled and used,
since we use pmic framework. So remove the code block.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Use pmic framework to simplify code and make code clean.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add android features booti, fastboot and recovery to i.MX6UL EVK board.
Since there is no user button on the board, we can't implement
the recovery by using button.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Correct USDHC Port Selection bits in bmode value for SD1 and SD2.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Correct the EIMNOR settings to non-mux mode and set the environment
variables configuration to FLASH when using WEIMNOR boot.
New target is added for build WEIMNOR boot u-boot:
mx6ul_ddr3_arm2_eimnor_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add board code for mx6ul ddr3 arm2 board.
QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR
Add sd1, qspi and spinor boot support
DDR script is 1.02 version.
Signed-off-by: Fugang Duan <b38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add BSP codes to support modules on the board:
I2C, SD/eMMC, NAND, QSPI, FEC1/FEC2, USB, LCDIF, 74LV, Serial
DDR version: 1.0
Build target: mx6ulevk_config
mx6ulevk_qspi1_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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We should not rely on pfuze_common_init to set the voltage,
may be we should remove the voltage settings in pfuze_common_init.
This patch is to setting the voltages in power_init_board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update IPU QoS settings from 0x007f007f to 0x77177717
according to the SoC team's recommendation. This change
should be able to balance AXI ID0/2/3 priority and set
AXI ID1 priority relatively lower, which matches the way
we use AXI ID0/1/2/3 for IDMAC23(0), regular IDMACs,
IDMAC27 and IDMAC28 respectively in kernel. The specific
priority values for each AXI ID are supposed to be picked
for the sake of an overall good system performance.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 7c4bee613dc47c9e2fb147a159236bca04b8618b)
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-Use the new pins' name for imx6dl.
-Change the read/write to registers by using register structure.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 66e7a93ff1e47d0e47627a984bcf2337db4f3bbf)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
board/freescale/mx6sabresd/mx6sabresd.c
Remove imx6dl part, since already fixed.
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Update to 1.05 ddr script, url:
http://compass.freescale.net/livelink/livelink?func=ll&
objId=233944823&objAction=browse&viewType=1
File name:
arik_r2_sabre_ddr3_528_1.05c.inc
Update:
Read latency
Aging control for IPU1/PRE0/PRE3
Aging control for IPU2/PRE1/PRE2
Test results:
3 boards passed overnight memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit b8625b732cfc59e44955f0e23b581e7896be1733)
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Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board,
but there is a problem in switching pre_periph_clk_sel to pll2_pfd2.
We cannot directly change the parent of pre_periph_clk_sel as this mux
is not a glitchless mux. We need to follow the correct procedure and wait
for the busy bits to clear before switching.
Change to follow the procedure:
1. Set periph_clk2 to OSC.
2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for periph_clk
, ahb_podf and axi_podf busy bits.
3. Setting the pre_periph_clk to PLL2 PFD 396M.
4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR busy bits.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 7490062ff86e1132b95bf153091f28f7940c0cf9)
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The LPDDR3 intialization in plugin codes were missed to update in previous
DDR script upgrading.
So update the plugin codes to LPDDR3 script: 7D_lpddr3_0_2.ds5
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 1874cec3a70adde2ea911a9c155fb41c43ccab61)
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[The compass link for this script]
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153
&objAction=browse&sort=name
[Changes in the script]
This script enable MDLL, but make it much more margin for the unlock state .
[DDR stress test result]
2 boards run the memtester for 3 days, and passed.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 6fa6765b0dcdad8d414931e49edf6ba65a73d23a)
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* Add mx7d_12x12_ddr3_arm2 target board support
* Initial support for mx7d_12x12_ddr3_arm2 target
board add support for base hardware eMMC, SD and
ECSPI boot.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 51d69f7996cc6e6da8bb3f0af751549cb2435e44)
Conflicts:
boards.cfg
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