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* powerpc/p2041rdb: update cpld reset command according to CPLD 2.0Shaohui Xie2011-10-03-7/+11
| | | | | | | | | CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driverYork Sun2011-09-29-11/+123
| | | | | | | | | | Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c. The unified driver can initialize data using DDR controller. No need to use DMA if just to initialze for ECC. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Refactor P2041RDB to use common p_corenet filesKumar Gala2011-09-29-202/+13
| | | | | | | | | | | The P2041RDB has almost identical setup for TLB, LAWS, and PCI with other P-Series CoreNet platforms. The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the TLB and LAW setup tables. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: refactor common P-Series CoreNet files for FSL boardsKumar Gala2011-09-29-5/+42
| | | | | | | | | | | | | | | | We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and P5020DS. There is a significant amount of commonality shared between these boards that we can refactor into common code: * Initial LAW setup * Initial TLB setup * PCI setup We start by moving the shared code between P3041DS, P4080DS, and P5020DS into a common directory to be shared with other P-Series CoreNet boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entriesKumar Gala2011-09-29-15/+19
| | | | | | | We shouldn't be setting execute permissions on TLB entries that will not actually have any code run from them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMMYork Sun2011-09-29-19/+84
| | | | | | | | | | | RDIMM has different timing parameters from UDIMM. Create new tables for RDIMMs. Single-, dual- and quad-rank RDIMMs have been verified with speeds from 800 to 1333MT/s. Speed table expands to include 1600MT/s for future use. Single- and quad-rank RDIMM entries are copied into UDIMM tables for future use. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Move DDR RCW overriding to common codeYork Sun2011-09-29-14/+0
| | | | | | | | DDR RCW varies at different speeds. It is common for all platform. Move it out from corenet_ds. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Cleanup extern in corenet_ds board codeKumar Gala2011-09-29-2/+1
| | | | | | Move extern of pci_of_setup() into corenet_ds.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: Add ethernet support on P2041RDB boardMingkai Hu2011-09-29-0/+230
| | | | | | | | | | | | | | Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board. The five dTSEC can be routed to two on-board RGMII phy, three on-board SGMII phy or four SGMII phy on SGMII riser card according to different serdes protocol configuration and board lane configuration. Also updated the device tree to direct the Fmac MAC to the correct PHY. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add networking support to P1023RDSRoy Zang2011-09-29-0/+40
| | | | | | | | | | | | | | | | | The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/hydra: Add ethernet support on P5020/P3041 DS boardsTimur Tabi2011-09-29-0/+555
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS & P5020DS ("Hydra"). The lane_to_slot[] array is initialized dynamically, since board switches can be used to control the muxing of SERDES lanes to slots. The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate slot. The SERDES configuration is queried to help determine the routing between MACs and slot/phy combination. If a XAUI card is inserted, muxing for that card is enabled and never turned off. The PHY address for the 10G XAUI card depends on the slot in which it's inserted. If it's in slot 1, the address is 4. If it's in slot 2, the address is 0. Update the MDIO routing in the P3041DS and P5020DS device trees based on the board-level muxing. The SERDES configuration determines which SGMII/XGMII boards are located in which slots, and so the MDIO bus needs to be muxed correctly whenever talking to a PHY connected to any Fman MAC. The Fman Ethernet nodes in the device tree also need to be routed to the correct PHYs. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add FMan ethernet support to P4080DSAndy Fleming2011-09-29-4/+632
| | | | | | | | | | | | | | | | | | | | | | | Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS. The board supports add-on cards for SGMII and XAUI functionality. Which slots on the board these cards are in is a function of the SERDES option selected and muxes on the board. Additionally because of the high-configurablity which MDIO bus one is connected to is "selected" via an FPGA register. We create dummy MDIO bus for the phy layer and hide the mux manipulation in this dummy layer. Add fman fdt helper function in board common code it'll be used by several freescale boards that do various muxing of the MDIO signals based on which controller/interface one is trying to talk to. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8548cds: Cleanup mpc8548cds.cZhao Chenhui2011-09-29-7/+0
| | | | | | | Remove unnecessary or dead code/includes. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entriesKumar Gala2011-09-29-15/+15
| | | | | | | We shouldn't be setting execute permissions on TLB entries that will not actually have any code run from them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add basic support for P1010RDBPoonam Aggrwal2011-09-29-0/+765
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for new P102x/P2020 RDB style boardsLi Yang2011-09-29-0/+946
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following boards share a common design but with minor variations between them: P1020MSBG-PC P1020RDB-PC P1020UTM-PC P1021RDB-PC P1024RDB P1025RDB P2020RDB-PC The P1020RDB-PC shares its roots in the existing P1020RDB board design, however uses DDR3 instead of DDR2. P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK. Key features on these boards include: * DDR3 * NOR flash * NAND flash (on RDB's only) * SPI flash (on RDB's only) * SDHC/MMC card slot * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) * PCIE slot and mini-PCIE slots As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM is used to store SPD data. In case of absent or corrupted SPD, falling back to timing data embedded in the source code will be used. Raw timing data is extracted from DDR chip datasheet. Different speeds of DDR are supported with this approach. ODT option is forced to fit this set of boards, again because they don't have regular DIMMs. CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification for writing timing. VSC firmware Address is defined by default in config file for eTSEC1. SD width is based off DIP switch. DIP switch is detected on the board by reading i2c bus and setting the appropriate mux values. Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have pins multiplexing. QE function needs to be disabled to access Nor Flash and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
* powerpc/mpc8610hpcd: set pci1_hose.config_table after fsl_setup_hoseZhao Chenhui2011-09-09-6/+5
| | | | | | | | The function fsl_setup_hose clears the variable pci1_hose. Set pci1_hose.config_table after it. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8548cds: set pci1_hose.config_table after fsl_setup_hoseZhao Chenhui2011-09-09-3/+3
| | | | | | | | The function fsl_setup_hose clears the variable pci1_hose. Set pci1_hose.config_table after it. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8568mds: set pci1_hose.config_table after fsl_setup_hoseZhao Chenhui2011-09-09-6/+5
| | | | | | | | The function fsl_setup_hose clears the variable pci1_hose. Set pci1_hose.config_table after it. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Makefile : fix generation of cpu related asm-offsets.hStefano Babic2011-09-07-1/+1
| | | | | | | | | | | commit 0edf8b5b2fa0d210ebc4d6da0fd1aceeb7e44e47 breaks building on a different directory with the O= parameter. The patch wil fix this issue, generating always asm-offsets.h before the other targets. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de> CC: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2011-09-04-673/+148
|\ | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-coldfire: ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usage ColdFire:Add mb for 5253 dram initialization ColdFire:Define the DM9000 byteswap for M5253 board. ColdFire:Update the env settings for several boards. ColdFire:disable the NFS define for 52277 board. ColdFire:Update the timer_init since it was unified. ColdFire: Cleanup for partial linking and --gc-sections ColdFire: Update compile flags for each CPUs ColdFire:Fix the configuration broken for some boards.
| * ColdFire:Add mb for 5253 dram initializationJason Jin2011-09-04-0/+4
| | | | | | | | | | | | | | | | The dram initialization sequence should be in order. This patch add mb for the dram intialization code to make sure the compiler do not disorder the code. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * ColdFire: Cleanup for partial linking and --gc-sectionsJason Jin2011-09-04-673/+144
| | | | | | | | | | | | | | | | Introduce the --gc-sections for ColdFire platform and clean up the corresponding lds file. Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* | MX5: mx51evk: make use of GPIO frameworkStefano Babic2011-09-04-13/+5
| | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* | MX35: mx35pdk: make use of GPIO frameworkStefano Babic2011-09-04-3/+2
| | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* | MX5: mx53loco: make use of GPIO frameworkStefano Babic2011-09-04-3/+3
| | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <r64343@freescale.com>
* | MX5: mx53evk: make use of GPIO frameworkStefano Babic2011-09-04-3/+3
| | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <r64343@freescale.com>
* | MX5: mx53smd: make use of GPIO frameworkStefano Babic2011-09-04-2/+2
| | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* | MX5: mx53ard: make use of GPIO frameworkStefano Babic2011-09-04-4/+4
| | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* | MX35: MX35PDK: support additional RAM on CSD1Stefano Babic2011-09-04-6/+20
| | | | | | | | | | | | | | Modules on mx35pdk have additional 128MB memory connected to CSD1. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | mx53: ddr3: Update DD3 initializationFabio Estevam2011-09-04-9/+9
|/ | | | | | | | | | | Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* video: Add SHARP LQ084S3LG01 LCD support on P1022DSTimur Tabi2011-08-04-2/+2
| | | | | | | | | | | | | | | | | The SHARP LQ084S3LG01 is a TFT LCD used on the P1022DS (revision "C") board. This device only supports 800x600 resolution, so if that resolution is selected, assume that this is the device. The device is attached to the LVDS port on the P1022DS board. The existing 800x600 entry (for the PDM360NG board) is actually 800x480, so we fix that. To support two different 800x resolutions, the Y-resolution is now passed to fsl_diu_init() and both values are used to pick the proper fb_videomode structure. The data for the 800x600 video mode is originally from Jiang Yutang. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com>
* powerpc/85xx: enable USB2 gadget mode for corenet ds boardShaohui Xie2011-07-29-0/+1
| | | | | | | | | | to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to 'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break out if it cannot find 'usb1', so drop the 'else' clause to make driver scan all the 'usbx'. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8xxx: drop redundant boot messagesWolfgang Denk2011-07-29-4/+4
| | | | | | | | | | | | | | | Current code would print RAM size information like this: DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Turn a number of printf()s into debug() to get rid of the redundant "DDR: " string like this: DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Adding configuration for DCSRCR to enable 32M accessStephen George2011-07-29-1/+2
| | | | | | | | | | | | | | | Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* cleanup: Fix typos and misspellings in various files.Mike Williams2011-07-28-1/+1
| | | | | | | | | | | Recieve/Receive recieve/receive Interupt/Interrupt interupt/interrupt Addres/Address addres/address Signed-off-by: Mike Williams <mike@mikebwilliams.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-07-18-10/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: ARM: MX5: Fix broken leftover TO-2 errata workaround MX31: Cleanup clock function scb9328: Add ARM relocation support am3517evm: change console device from ttyS2 to ttyO2 Remove volatile qualifier in get_ram_size() calls TI: TNETV107X Fix Build Error ARM: add missing CONFIG_SKIP_LOWLEVEL_INIT for armv7 arm: add CONFIG_MACH_TYPE setting and documentation arm: add __ilog2 function Timer: Fix misuse of ARM *timer_masked() functions outside arch/arm EfikaMX: Enable EXT2 booting EfikaMX: Add missing CONFIG_SYS_TEXT_BASE EfikaMX: Use correct imximage.cfg MX27: Update to autogenerated asm-offsets.h MX5: Update to autogenerated asm-offsets.h imx: Add support for zmx25 board imx: Make imx25 compatible to mxc_gpio driver and fix in tx25 imx: Add auto generation of asm-offsets.h for imx25 imx: Add support for USB EHCI on imx25 imx: Use correct imx25 reset.c imx: Add get_tbclk() function for imx25 ARM: Update maintainer of board scb9328 mx27: Make the UART port number explicit build: Add targets for auto gen of asm-offsets.h and use it in imx35 mx31pdk: cosmetic: Fix line over 80 characters
| * Remove volatile qualifier in get_ram_size() callsAlbert ARIBAUD2011-07-17-10/+10
| | | | | | | | | | | | | | | | | | Checkpatch.pl complains about the volatile qualifier in calls to get_ram_size(). Remove this qualifier in the prototype and in the calls where it is useless, and leave it only in the function body where it is needed. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | powerpc/p2041rdb: Add p2041rdb board supportMingkai Hu2011-07-17-0/+793
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | P2041RDB Specification: ----------------------- Memory subsystem: * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) * 128 Mbyte NOR flash single-chip memory * 256 Kbit M24256 I2C EEPROM * 16 Mbyte SPI memory * SD connector to interface with the SD memory card Ethernet: * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) PCIe: * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces I2C: * I2C1: Real time clock, Temperature sensor, Memory module * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2 UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* qoriq/p1_p2_rdb: USB device-tree fixups for P1020Ramneek Mehresh2011-07-11-0/+47
| | | | | | | | | | Resolve P1020 second USB controller multiplexing with eLBC - mandatory to mention USB2 in hwconfig string to select it over eLBC, otherwise USB2 node is removed - works only for SPI and SD boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add basic support for P1023RDS boardRoy Zang2011-07-11-0/+406
| | | | | | | | | | | | | | The P1023RDS board is the reference board for the P1023 SoC. Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe, UART, I2C, etc. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc85xx: Display a warning for unsupported DDR data ratesYork Sun2011-07-11-4/+21
| | | | | | | | If DDR initialziation uses a speed table and the speed is not matched, print a warning message instead of silently ignoring. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/corenet_ds: Fix RCW overriding for RDIMMYork Sun2011-07-11-1/+1
| | | | | | | Allow overriding RCW for all RDIMM, not only quad-rank ones. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: display boot device and bank on the MPC8610 HPCDTimur Tabi2011-07-11-2/+23
| | | | | Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't setKumar Gala2011-07-11-0/+2
| | | | | | | | | | | Add ifdef protection for qp_info and liodn associated with Q/BMan. Also rearrange setting of _tbl_sz variables to utilize existing ifdef protection for things like FMAN. Also add protection around setup_portals() call in corenet_ds board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_{B,Q}MAN_MEM_PHYS aren't setKumar Gala2011-07-11-0/+8
| | | | | | | | Add ifdef protection in LAW & TLB code to handle the case in which CONFIG_SYS_BMAN_MEM_PHYS or CONFIG_SYS_QMAN_MEM_PHYS arent defined for a build. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/83xx: remove empty board_early_init_f()Timur Tabi2011-07-06-10/+0
| | | | | | | Remove an empty board_early_init_f() from the MPC8323ERD and MPC360ERDK boards. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MX53: Add initial support for MX53ARDFabio Estevam2011-07-04-0/+450
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* powerpc/p1022ds: set the clock-frequency prop only if the clock is enabledTimur Tabi2011-06-09-6/+10
| | | | | | | | | | | The clock-frequency property in an audio codec's device tree node is set to the input clock frequency for that codec. On the Freescale P1022DS board, the input clock is enabled only if the hwconfig 'audclk' option is set. Therefore, the property should only be set in the device tree if the clock is actually enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mx31ads: Use the new relocation schemeFabio Estevam2011-06-06-14/+48
| | | | | | | This fixes the MX31ADS build by using the new relocation scheme. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Felix Radensky <felix@embedded-sol.com>
generated by cgit v1.1 at 2024-10-06 15:19:34 +0000