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* MLK-11228-1 android: Integrate community fastboot with FSL i.MX fastbootYe.Li2015-07-13-164/+80
| | | | | | | | | | | | | | | | | | | | | 1. Replace the UDC driver with community's USB gadget d_dnl driver. 2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and EFI partitions are not support by i.MX. 3. Add FDT support to community's android image. 4. Change the booti command to boota, due to the booti has been used for ARM64 image boot. 5. Modify boota implementation to load ramdisk and fdt to their loading addresses specified in boot.img header, while bootm won't do it for android image. 6. Modify the android image HAB implementation. Authenticate the boot.img on the "load_addr" for both SD and NAND. 7. Enable new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot with relevant header file "fsl_fastboot.h". While disabling the configuration, the community fastboot is used. 8. Use community's way to combine cmdline in boot.img and u-boot environment, not overwrite the cmdline in boot.img Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11237 imx: mx6qpsabreauto update ddr script to 1.07Peng Fan2015-07-13-2/+8
| | | | | | | | | | | | | | | Update ddr script to version 1.07: 1. Change MDCCR from default value to 0x24912492, it will improve DDR duty cycle 2. The MMDC reorder bypass option, which has better DRAM performance URL: http://compass.freescale.net/livelink/livelink?func=ll&objId=234335046&objAction=browse&viewType=1 Test Results: 3 boards passed 48 hours memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11230 imx6: USB: Modify OTG ID pin pad setting to pull upYe.Li2015-07-09-14/+54
| | | | | | | | | | Set the ID pin pad to pull up not the pull down at default, otherwise we can't enter the device mode, but always detect as host. After this change we have to use portA cable to play as host, and use portB cable for device. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11227 imx: mx6ul_14x14_lpddr2_arm2 add weimnor defconfigPeng Fan2015-07-09-0/+6
| | | | | | | | | | | | | 1. Add weimnor boot defconfig 2. move CONFIG_FSL_USDHC and CONFIG_VIDEO to board header 3. Add CONFIG_SYS_FLASH_PROTECTION for mx6ul 14x14 lpddr2 arm2 4. correct CONFIG_SYS_FLASH_SECT_SIZE and CONFIG_SYS_MAX_FLASH_SECT 5. Add comments for setup_eimnor, since ENET2_RXER pin conflicts with ENET2. Also eimnor support will disable SD1/SD2, need ENET to boot kernel and nfs using enet. So setup_eimnor should be invoked after setup_fec Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11217 imx: mx6ul: Modify QSPI PAD DSE to 120ohmYe.Li2015-07-03-3/+3
| | | | | | | | The current pad DSE for QSPI is 60ohm. Per hardware team measurement, this setting cause too strong drive to clock and data signals. Need to change the DSE to 120ohm for better signal quality. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11216-2 imx: mx7d-ddr3 remove epdc qos settingsPeng Fan2015-07-03-48/+0
| | | | | | Remove epdc qos settings from plugin.S, since set_epdc_qos does same thing. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11216-1 imx:mx7d_12x12_ddr3_arm2 add missed Kconfig filesPeng Fan2015-07-03-0/+15
| | | | | | Add missed Kconfig files for mx7d_12x12_ddr3_arm2 board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11135-2 imx: mx6ul: Add MX6UL LPDDR2 ARM2 board supportYe.Li2015-06-19-0/+1282
| | | | | | | | | Add MX6UL LPDDR2 ARM2 board BSP codes, supported peripherals: SD1, eMMC(USDHC2), USB OTG1, I2C, ENET2, PMIC. Due to a board issue, the SD1 only supports 1 bit bus width. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11134-2 imx: mx7d_12x12_ddr3_arm2 update spi nor codePeng Fan2015-06-19-0/+5
| | | | | | | We should use board_spi_cs_gpio and remove the GPIO from CONFIG_SF_DEFAULT_CS. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11059 imx: HAB unable to support Encrypted boot for 4096-bit keysUlises Cardenas2015-06-16-24/+24
| | | | | | | | Abstracted the CSF size in imximage from a hardcoded value to a config setting CONFIG_CSF_SIZE. This configuration is only enabled for secure boot. Increased the size of the CSF default allocation to 0x4000. This size covers the event the worst case of 4906-bits keys.
* MLK-11099 imx: mx6ul: Enable the Watchdog WDOG_B signal outputYe.Li2015-06-12-0/+2
| | | | | | | | When using watchdog timeout in kernel, the reset does not output the WDOG_B signal, so the power supply won't be reset. To solve the problem, we enable it in u-boot. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11033 imx: mx7d: Update the lpddr3 script to 3.0.3 revYe.Li2015-06-04-4/+4
| | | | | | | | | | | | | | | | | | Update the DDR script for i.MX7D 12x12 LPDDR3 ARM2 board and i.MX7D 19x19 LPDDR3 ARM2 board to file "7D_lpddr3_0_3.ds5" Updated items: Changes DRAMTMG2 WR2RD from 7 to 8. Compass link for this script: http://compass.freescale.net/livelink/livelink?func=ll &objid=233861153&objAction=browse&sort=name Test results: Passed overnight test on two MX7D 12x12 LPDDR3 ARM2 board Passed overnight test on one MX7D 19x19 LPDDR3 ARM2 board Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11036 imx: mx6ul fix plugin build fail and update ddrPeng Fan2015-06-04-5/+9
| | | | | | | | | | Since directory name changed, need to change it in imximage.cfg, or we will get "Can't stat board/freescale/mx6ulevk/plugin.bin". Since this commit 7331a4cc0853722b4c3addf1927a2797f39f5de2 missed to update ddr, here update the plugin code. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11011 imx: mx6ul-14x14-evk update ddr version to 1.1Peng Fan2015-06-02-4/+4
| | | | | | | | | | | | | | | | | | | | updated DDR Script of 6UL EVK Board to avoid a calibration error when using “DDR_Stress_Tester_V1.04.exe”. Updated items: [Modified] setmem /32 0x020E027C = 0x00000008 [Modified] setmem /32 0x020E0280 = 0x00000038 [Modified] setmem /32 0x021B080C = 0x00070007 [Added ] setmem /32 0x021B0858 = 0x00000F00 The script versions of EVK board and Validation Board from the following link: http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj Action=browse&viewType=1 Test Results: Tested on two boards, both passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11010 imx: mx7d: Fix EIMNOR lock issue on mx7d 19x19 lpddr3 boardYe.Li2015-06-01-0/+1
| | | | | | | | | | Since the flash blocks are locked at default , need to set "CONFIG_SYS_FLASH_PROTECTION" to unlock them before write/erase. The patch also add the pinmux for LBA (ADV) pin and set eimnor enabled at default. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11008 imx: HAB: Fix secure boot configuration and build issueYe.Li2015-06-01-1/+1
| | | | | | | | | | | 1. There is conflict when building secure boot, because some common codes for MPC are included by using same configuration. So modify the makefile to get rid of them. 2. The 6UL arch config is missed in hab.h. Fix this issue by using the CONFIG_ROM_UNIFIED_SECTIONS. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10972-2 imx: mx7dsabresd fix i2c index usagePeng Fan2015-05-26-1/+1
| | | | | | i2c_pad_info3's i2c index should 2, but not 1. Correct it. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10956 imx: mx6ul: Change BSP name and dtb name for 14x14 packageYe.Li2015-05-25-10/+10
| | | | | | | | | | | | | | Since there is another 9x9 package for mx6ul, modify the BSP names of ddr3 arm2 board and evk board to add 14x14 package info. Also modify the loaded dtb file to align with kernel. After the change, the build target for mx6ul ddr3 arm2 board is: mx6ul_14x14_ddr3_arm2_config and the build target for mx6ul evk board is: mx6ul_14x14_evk_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10936 imx: mx7d: Change to use bootrom_sw_info for getting boot deviceimx_3.14.38_6ul_engrYe.Li2015-05-20-40/+25
| | | | | | | | | | | | | | | | | | | | | On MX7D, boot rom can provide some boot information such as boot device, arm freq, axi freq, etc. (see the structure below) Offset Byte4 | Byte3 | Byte2 | Byte1 0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved 0x4 ARM core frequency(in Hz) 0x8 AXI bus frequency(in Hz) 0x0C DDR frequency(in Hz) 0x10 GPT1 input clock frequency(in Hz) 0x14 Reserved 0x18 0x1C The boot information can be accessed by get the pointer at 0x1E8. This patch changes the u-boot to use the new approach. When manufacture boot, the info recorded is the actual SD port, not the failed device. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10885 imx: mx6slevk ignore elan init when no epdc on boardPeng Fan2015-05-14-13/+21
| | | | | | | | | | | | | | | | If no epdc pannel is plugged into mx6slevk board, no need to do the elan init operation for each i2c init transfer which will slow the i2c speed. If epdc panned is plugged into mx6slevk board, all works as the original patch: "b6ba68516b681a38025252bd0ef6a6ed3e8adfa0" - "MLK-10215 Add elan init in i.MX6SL-EVK board" This patch also fix a bug that setup_elan_pads should be called in board_init, but not board_late_init where too late to setup_elan_pads. And align pad property with linux kernel, value is 0x17000. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10839: arm: imx: mx7d 19x19 lpddr3 arm2 board supportAdrian Alonso2015-05-13-0/+968
| | | | | | | | | | | | | * Add mx7d_19x19_lpddr3_arm2 target board supprt * Enable i2c, spinor, usb, usdhc, qspi, enet, uart * Build targets mx7d_19x19_lpddr3_arm2_defconfig mx7d_19x19_lpddr3_arm2_eimnor_defconfig - Set EIMNOR settings for Intel Sibley Asynchronous mode - Set flash sector size for 256kb (erase block size) Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10873-2 imx:mx6ul removed uncompiled pmic codePeng Fan2015-05-11-8/+0
| | | | | | | This piece of code will never be compiled and used, since we use pmic framework. So remove the code block. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10873-1 imx:mx7d use pmic frameworkPeng Fan2015-05-11-82/+50
| | | | | | Use pmic framework to simplify code and make code clean. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10865 imx: mx6ulevk: Add android supportYe.Li2015-05-08-0/+110
| | | | | | | | Add android features booti, fastboot and recovery to i.MX6UL EVK board. Since there is no user button on the board, we can't implement the recovery by using button. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10855 imx: mx6ulevk/ddr3_arm2: Fix bmode value for SD1 and SD2Ye.Li2015-05-07-3/+3
| | | | | | Correct USDHC Port Selection bits in bmode value for SD1 and SD2. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10841 imx: mx6ul_ddr3_arm2: Add support for WEIMNOR bootYe.Li2015-05-07-4/+4
| | | | | | | | | | Correct the EIMNOR settings to non-mux mode and set the environment variables configuration to FLASH when using WEIMNOR boot. New target is added for build WEIMNOR boot u-boot: mx6ul_ddr3_arm2_eimnor_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10817 imx:mx6ul_ddr3_arm2 add mx6ul ddr3 arm2 board supportPeng Fan2015-05-05-0/+1308
| | | | | | | | | | | | | Add board code for mx6ul ddr3 arm2 board. QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR Add sd1, qspi and spinor boot support DDR script is 1.02 version. Signed-off-by: Fugang Duan <b38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10821 imx: mx6ulevk: Add board support for mx6ulevkYe.Li2015-05-05-0/+1160
| | | | | | | | | | | Add BSP codes to support modules on the board: I2C, SD/eMMC, NAND, QSPI, FEC1/FEC2, USB, LCDIF, 74LV, Serial DDR version: 1.0 Build target: mx6ulevk_config mx6ulevk_qspi1_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10774-53 imx: update setting pmic volatagePeng Fan2015-04-29-7/+178
| | | | | | | | We should not rely on pfuze_common_init to set the voltage, may be we should remove the voltage settings in pfuze_common_init. This patch is to setting the voltages in power_init_board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10733 imx: imx6qpsabreauto: Update IPU QoS settingsLiu Ying2015-04-29-3/+3
| | | | | | | | | | | | | | Update IPU QoS settings from 0x007f007f to 0x77177717 according to the SoC team's recommendation. This change should be able to balance AXI ID0/2/3 priority and set AXI ID1 priority relatively lower, which matches the way we use AXI ID0/1/2/3 for IDMAC23(0), regular IDMACs, IDMAC27 and IDMAC28 respectively in kernel. The specific priority values for each AXI ID are supposed to be picked for the sake of an overall good system performance. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 7c4bee613dc47c9e2fb147a159236bca04b8618b)
* ENGR00315894-34 imx6:dlsabresd/slevk Fix build break when enables EPDCYe.Li2015-04-29-11/+14
| | | | | | | | | | | | | -Use the new pins' name for imx6dl. -Change the read/write to registers by using register structure. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 66e7a93ff1e47d0e47627a984bcf2337db4f3bbf) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: board/freescale/mx6sabresd/mx6sabresd.c Remove imx6dl part, since already fixed.
* MLK-10674-1 imx: mx6qpsabreauto Update to 1.05 DDR ScriptPeng Fan2015-04-29-1/+9
| | | | | | | | | | | | | | | | | | | | Update to 1.05 ddr script, url: http://compass.freescale.net/livelink/livelink?func=ll& objId=233944823&objAction=browse&viewType=1 File name: arik_r2_sabre_ddr3_528_1.05c.inc Update: Read latency Aging control for IPU1/PRE0/PRE3 Aging control for IPU2/PRE1/PRE2 Test results: 3 boards passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b8625b732cfc59e44955f0e23b581e7896be1733)
* MLK-10504 imx: mx6dqarm2: Fix CCM setting for lpddr2 400Mhz supportYe.Li2015-04-29-0/+6
| | | | | | | | | | | | | | | | | | Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board, but there is a problem in switching pre_periph_clk_sel to pll2_pfd2. We cannot directly change the parent of pre_periph_clk_sel as this mux is not a glitchless mux. We need to follow the correct procedure and wait for the busy bits to clear before switching. Change to follow the procedure: 1. Set periph_clk2 to OSC. 2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for periph_clk , ahb_podf and axi_podf busy bits. 3. Setting the pre_periph_clk to PLL2 PFD 396M. 4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR busy bits. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 7490062ff86e1132b95bf153091f28f7940c0cf9)
* MLK-10658 imx: mx7d 12x12 arm2: Update plugin codes to use latest DDR scriptYe.Li2015-04-29-23/+27
| | | | | | | | | | The LPDDR3 intialization in plugin codes were missed to update in previous DDR script upgrading. So update the plugin codes to LPDDR3 script: 7D_lpddr3_0_2.ds5 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 1874cec3a70adde2ea911a9c155fb41c43ccab61)
* MLK-10617 imx: mx7d 12x12 arm2: Update LPDDR3 script to 7D_lpddr3_0_2.ds5Ye.Li2015-04-29-1/+1
| | | | | | | | | | | | | | | [The compass link for this script] http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153 &objAction=browse&sort=name [Changes in the script] This script enable MDLL, but make it much more margin for the unlock state . [DDR stress test result] 2 boards run the memtester for 3 days, and passed. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6fa6765b0dcdad8d414931e49edf6ba65a73d23a)
* MLK-10522-3: imx: mx7d_12x12_ddr3_arm2: add target board supportAdrian Alonso2015-04-29-0/+687
| | | | | | | | | | | | | | * Add mx7d_12x12_ddr3_arm2 target board support * Initial support for mx7d_12x12_ddr3_arm2 target board add support for base hardware eMMC, SD and ECSPI boot. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 51d69f7996cc6e6da8bb3f0af751549cb2435e44) Conflicts: boards.cfg
* MLK-10568 imx: mx7d arm2: Update LPDDR3 script to 7D_lpddr3_0_1.ds5Ye.Li2015-04-29-19/+16
| | | | | | | | | | | | | | | | | | | | | | [The compass link for this script] http://compass.freescale.net/livelink/livelinkfunc=ll&objid=233861153 &objAction=browse&sort=name [Changes in the script] 1. Change the DDR freq to 528Mhz. 2. Disable ddr phy dll, just force a dll output. IC suspects the dll in ddr phy may unlock sometimes. The side-effect is we will lost the ability to compensate the voltage/temperature change, so it may easy to fail at H/L temperature. [DDR stress test result] 3 boards involved the two days stress test by using memtester tool. One board met a kernel oops after one day test. Other two pass the two days test. Compared to previous DDR script, the result is much positive. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 843c3c54af12cbf20e7bc912178e5a3628b78198)
* MLK-10567: Extend u-boot imximage to support check bits set/clrNitin Garg2015-04-29-7/+7
| | | | | | | | | | | Add support for HAB "Check data" all bits set and clear check functionality. Rename CHECK_DATA to CHECK_BITS_SET. Flag=0 -> (*address & mask) == 0 | All bits clear Flag=2 -> (*address & mask) == mask | All bits set Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 0836912ef7a53d1f3d65f95556a34d03b8d65399)
* MLK-10774-41 imx: mx6sx: update VDDSOC standby voltagePeng Fan2015-04-29-0/+18
| | | | | | | | | | | | | This patch is from commit "f2c5102bf3763d77a227c1cba7fcd49e3db53a1d". " According the latest datasheet Rev.0,2/2015, the VDDSOC_IN voltage in standby/DSM mode is 1.05V. As we use PFM mode of pFuse and this mode has 3% tolerance issue, so the standby mode voltage should be (1.05 * 1.03) = 1.0815, we use 1.10V as the minimal step is 25mV. For i.MX6sx SDB RevB boards, the VDDARM and VDDSOC use the same supply, so the DSM voltage for VDDARM also need to be updated. " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10492-2 imx: mx7dsabresd: Add TFT43AB LCD supportYe.Li2015-04-29-9/+9
| | | | | | | | The mx7dsabresd uses new LCD TFT43AB which has 480 x 272 pixels. Update panel info for this LCD. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit e77d667b20956a37de9d367a8914ef2fe79258df)
* MLK-10477-5 imx: mx7dsabresd: Add EPDC supportYe.Li2015-04-29-75/+250
| | | | | | | | | | | | | | | | To enable the EPDC feature: 1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings in mx7dsabresd.h 2. cd <kernel_dir>/firmware/imx 3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin 4. cp epdc_splash.bin to [FAT partition on SD card] Since the EPDC has pinmux conflicts with ENET and QSPI. These two modules can't work at same time. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 8ba7f88f9efac9f90319b71644d3d1191f535d03)
* MLK-10477-4 imx: mx7d 12x12 lpddr3 ARM2: Add EPDC supportYe.Li2015-04-29-0/+257
| | | | | | | | | | | | | To enable the EPDC feature: 1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings in mx7d_12x12_lpddr3_arm2.h 2. cd <kernel_dir>/firmware/imx 3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin 4. cp epdc_splash.bin to [FAT partition on SD card] Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 414824dcb77a067213849d340cf92777e6546810)
* MLK-10478 mx6: EPDC: Improve EPDC usage and configurationYe.Li2015-04-29-145/+53
| | | | | | | | | | | | | | Change to load EPDC waveform from FAT partition and allocate waveform buffer, framebuffer and working buffer in dynamic manner not static. So many EPDC configurations are removed. To enable the EPDC feature, must define CONFIG_MXC_EPDC and CONFIG_SPLASH_SCREEN. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 4d55a4124be3a3a6288c3c845d17fd9d4f2b8b43) Conflicts: include/configs/mx6slevk.h
* MLK-10476 imx: mx7dsabresd: Fix 74LV driver issueYe.Li2015-04-29-8/+9
| | | | | | | | | Should write the bits to SDI in reverse order because of the bits will be shifted. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 83389e054d3cb7a905a3f81c20f395e784beb258) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-39 imx:mx6qsabreauto update video settingsPeng Fan2015-04-29-7/+91
| | | | | | Update video settings Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-38 imx: fix ecspi codePeng Fan2015-04-29-0/+20
| | | | | | | | | | | This commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 "spi: mxc: fix sf probe when using mxc_spi" introduces "board_spi_cs_gpio" function to discard gpio in CONFIG_SF_DEFAULT_CS for spi flash. Follow this rule to make imx boards work fine. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10448-6 imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board supportYe.Li2015-04-29-1/+339
| | | | | | | | | | | | | | | | | | 1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit e0b316f071aa17c8e41a50f395346ab9f012e665) Conflicts: board/freescale/mx6qsabreauto/mx6qsabreauto.c boards.cfg
* MLK-10446: mx7d_12x12_lpddr3_arm2: Enable 1.8V on PHY ctrlFabio Estevam2015-04-29-2/+0
| | | | | | | | | | Enable 1.8V on PHY control, so that Gigabit PHY operation can be functional. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit a17f1300a1b6d3b46a090baa84ba2fef104a1af6) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-37 imx:mx7d fix qspi probe errorPeng Fan2015-04-29-6/+6
| | | | | | We should use CONFIG_FSL_QSPI, but not CONFIG_QSPI Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-35 imx:mx7 use power_init_boardPeng Fan2015-04-29-80/+48
| | | | | | | Upgrade to upstream way, using power_init_board. Add pfuze300 support. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
generated by cgit v1.1 at 2024-11-09 14:22:04 +0000