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* MLK-10774-5 Add EPDC splash screen for MX 6DL SabreSD and 6SL EVKPeng Fan2015-04-29-0/+657
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add EPDC splash screen feature for MX6SL EVK, and MX6DL SABRESD board. - Currently, splash screen consists of a simple black border around a white screen. Done this way to save in memory footprint. - EPDC splash screen is disabled by default in the config file for MX6DL_SABRESD and MX6SL_EVK. If left enabled, the U-Boot image will not boot correctly (hang), since some additional content on the boot device (waveform file) is required for EPDC splash to work correctly. Please refer to Linux Reference Manual for how to flash WAVEFORM file. Signed-off-by: Robby Cai <R63905@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit b8ab9b3eabb94bbbc1eea63e7c0e2a87d2d645f4) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: arch/arm/include/asm/arch-mx6/mx6sl_pins.h board/freescale/mx6sabresd/mx6sabresd.c board/freescale/mx6slevk/mx6slevk.c drivers/video/Makefile include/configs/mx6sabresd.h include/configs/mx6slevk.h include/lcd.h drivers/video/Makefile
* MLK-10774-2 HDMI: splash screen function enhancementPeng Fan2015-04-29-10/+10
| | | | | | | | | | | | | | -Change HDMI video mode to VGA. -Add pixel clock fraction part setting in IPU driver, fix video mode timing issue. -Add overflow state clear workaround, fix kernel hang in HDMI driver issue. -Correct IPU clock to 264MHz. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 45d532a0237f5baf2ec95b4364ec5bc94d312689) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-04-13-1/+0
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| * mx53loco: Disable printing cpuinfoFabio Estevam2015-04-08-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 32df39c741788e ("mx5: fix get_reset_cause") we have the following boot messages on a mx53qsb: U-Boot 2015.04-rc5-00029-gd68df02 (Apr 06 2015 - 11:15:39) CPU: Freescale i.MX53 rev2.1 at 800 MHz Reset cause: POR Board: MX53 LOCO I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial CPU: Freescale i.MX53 rev2.1 at 1000 MHz Reset cause: unknown reset Net: FEC [PRIME] The CPU and Reset cause lines appear twice. Initially mx53 boots at 800MHz, then at a later point the PMIC is configured via I2C to raise the CPU voltage so that it can run at 1GHz. To avoid such misleading double printings, disable printing cpu info for now. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Jason Liu <r64343@freescale.com>
* | m68k: fix 3 broken boardsangelo@sysam.it2015-03-28-2/+0
|/ | | | | | | | | | | Fix eb_cpu5282 and eb_cpu5282_internal unresolved external error. These boards have video but don't need any ppc related video_setmem(). Fix M53017EVB moving away embedded env to a different offset, as in M52277EVB. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-03-05-44/+880
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| * SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.gaurav rana2015-03-05-0/+6
| | | | | | | | | | | | | | | | | | | | esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * SECURE BOOT: Add command for validation of imagesgaurav rana2015-03-05-0/+874
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. esbc_validate command is meant for validating header and signature of images (Boot Script and ESBC uboot client). SHA-256 and RSA operations are performed using SEC block in HW. This command works on both PBL based and Non PBL based Freescale platforms. Command usage: esbc_validate img_hdr_addr [pub_key_hash] 2. ESBC uboot client can be linux. Additionally, rootfs and device tree blob can also be signed. 3. In the event of header or signature failure in validation, ITS and ITF bits determine further course of action. 4. In case of soft failure, appropriate error is dumped on console. 5. In case of hard failure, SoC is issued RESET REQUEST after dumping error on the console. 6. KEY REVOCATION Feature: QorIQ platforms like B4/T4 have support of srk key table and key revocation in ISBC code in Silicon. The srk key table allows the user to have a key table with multiple keys and revoke any key in case of particular key gets compromised. In case the ISBC code uses the key revocation and srk key table to verify the u-boot code, the subsequent chain of trust should also use the same. 6. ISBC KEY EXTENSION Feature: This feature allows large number of keys to be used for esbc validation of images. A set of public keys is being signed and validated by ISBC which can be further used for esbc validation of images. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx/t104xrdb : remove raw timing parametervijay rai2015-03-05-44/+0
| | | | | | | | | | | | | | | | This board uses DDR DIMM. Reading SPD provides more flexibility. Raw timing parameter code should be removed after debugging. Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-03-05-21/+105
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| * mx5: fix get_reset_causeStefano Babic2015-03-05-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | commit d9f43c8f5c1d7ed27c99a06be85a4bb64b2c73fb sets get_reset_cause() as static, but this conflicts with mx5 where its prototype is in sys_proto.h. Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco, factorizing the call for this board. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <jason.hui@linaro.org>
| * mx6slevk: Provide a proper pad configuration for OTG1_ID pinFabio Estevam2015-03-02-1/+6
| | | | | | | | | | | | | | Pass the same pad configuration as done in the kernel so that OTG1_ID pin can properly work in device mode. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx25pdk: Turn on the LCD supplyFabio Estevam2015-03-02-2/+2
| | | | | | | | | | | | | | | | | | Currently there is no support for MC34704 PMIC in the mainline kernel. Turn on the LCD supply via bootloader for the time being, so that we could use the LCD in the kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-02-4/+83
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| * | imx:mx6slevk implement power init boardPeng Fan2015-02-23-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement power_init_board and related I2C interface configuration. After adding this, uboot can successfully detect and configure pmic. " U-Boot 2015.01-00281-ge29eddf (Feb 12 2015 - 09:24:01) CPU: Freescale i.MX6SL rev1.0 at 396 MHz Reset cause: POR Board: MX6SLEVK I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-02-13-3413/+525
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| * | | imx:mx6 set normal APS and standby PFM modePeng Fan2015-02-11-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To normal mode, use APS switching mode. To standy mode, use PFM switching mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * | | pmic:pfuze implement pmic_mode_initPeng Fan2015-02-11-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to implement pmic_mode_init function, and add prototype in header file. This function is to set switching mode for pmic buck regulators to improve system efficiency. Mode: OFF: The regulator is switched off and the output voltage is discharged. PFM: In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency. PWM: In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS: In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
* | | | mpc837xerdb: "fix Calling __hwconfig without a buffer" warningSinan Akman2015-03-02-1/+6
| |_|/ |/| | | | | | | | Signed-off-by: Sinan Akman <sinan@writeme.com>
* | | arm: ls1021x: Add support for initializing CAAM's stream idAlison Wang2015-02-24-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | drivers/mc: Migrated MC Flibs to 0.5.2J. German Rivera2015-02-24-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | ARMv8/LS2085A: Enable auto precharge for DP-DDRYork Sun2015-02-24-0/+1
| | | | | | | | | | | | | | | | | | | | | DP-DDR benefits from auto precharge because of its specific application. Signed-off-by: York Sun <yorksun@freescale.com>
* | | armv8/ls2085a: Enable cluster timebase for all clustersYork Sun2015-02-24-2/+9
| |/ |/| | | | | | | | | | | LS2085A and its variants can have up to four clusters. It is safe to enable timebase for all even some may be disabled. Signed-off-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-02-10-28/+172
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| * mx53loco: Fix boot hang during reboot stress testFabio Estevam2015-02-10-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently by running the following test: => setenv bootcmd reset => save => reset , we observe a hang after approximately 20-30 minutes of stress reboot test. Investigation of this issue revealed that when a single DDR chip select is used, the hang does not happen. It only happens when the two chip selects are active. MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence": "The controller must keep the memory lines quiet (except for CK) for the ZQ calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256 for other ZQCL and 64 for ZQCS)." According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL: "Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines. Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)" So make sure to activate one chip select at time (CS0 first and then CS1 later), so that the required JEDEC delay is respected for each chip select. With this change applied the board has gone through three days of reboot stress test without any hang. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6qsabreauto: Change to use common GPMI IO clock functionYe.Li2015-02-10-23/+2
| | | | | | | | | | | | | | | | Since a clock function setup_gpmi_io_clk is implemented for GPMI IO clock settings, change to use this common function in GPMI setup. Signed-off-by: Ye.Li <B37916@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx:mx6sxsabresd board spl supportPeng Fan2015-01-22-0/+169
| | | | | | | | | | | | Add board level spl support for mx6sxsabresd board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * mx6sxsabresd: Remove unneeded board_late_init()Fabio Estevam2015-01-19-5/+0
| | | | | | | | | | | | | | | | Since commit 1f98e31bc0b2c37a ("imx: mx6sxsabresd: Use the pfuze common init function") board_late_init() became empty, so we can safely remove this unneeded function. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | fsl/ls1021qds: Add deep sleep supporttang yuantian2015-01-24-0/+43
| | | | | | | | | | | | | | | | Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
* | arm: ls102xa: Add LPUART support for LS1021ATWR boardAlison Wang2015-01-23-0/+1
| | | | | | | | | | | | | | | | This patch adds LPUART support for LS1021ATWR board. For ls1021atwr_nor_lpuart_defconfig, LPUART is used as the console. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | arm: ls102xa: Add LPUART support for LS1021AQDS boardAlison Wang2015-01-23-0/+1
| | | | | | | | | | | | | | | | This patch adds LPUART support for LS1021AQDS board. For ls1021aqds_nor_lpuart_defconfig, LPUART is used as the console. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | arm: ls102xa: Update snoop settings for CCI-400Alison Wang2015-01-23-17/+29
| | | | | | | | | | | | | | | | | | | | | | CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. These CCI-400 operations are moved to board_early_init_f() to be initialized earlier. For S4 slave interface, issuing of snoop requests and DVM message requests are enabled. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ls102xa: dcu: Add platform support for DCU on LS1021AQDS boardXiubo Li2015-01-23-0/+99
| | | | | | | | | | | | | | | | | | | | This patch adds the CH7301 HDMI options and the common configuration for DCU on LS1021AQDS board. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Cc: Jason Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as defaultAlison Wang2015-01-23-1/+34
| | | | | | | | | | | | | | | | | | | | This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will be used via hwconfig. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc: mpc85xx: remove P2020DS board supportMasahiro Yamada2015-01-23-536/+0
| | | | | | | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | powerpc: mpc85xx: remove P2020COME board supportMasahiro Yamada2015-01-23-439/+0
| | | | | | | | | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Ira W. Snyder <iws@ovro.caltech.edu>
* | powerpc: mpc85xx: remove P1_P2_RDB boardsMasahiro Yamada2015-01-23-1108/+0
| | | | | | | | | | | | | | | | These boards are still non-generic boards: P1011RDB, P1022RDB, P2010RDB, P2020RDB Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* | powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS supportMasahiro Yamada2015-01-23-1259/+1
| | | | | | | | | | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Dave Liu <daveliu@freescale.com> Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-01-22-45/+315
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| * | board/T1040rdb: Add VSC9953 support for T1040rdb boardCodrin Ciubotariu2015-01-21-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | This patch configures and initializes the L2 switch on T1040rdb board. The external L2 switch ports may be connected to PHYs only over QSGMII, for T1040rdb. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
| * | board/T1040qds: Add VSC9953 support for T1040qds boardCodrin Ciubotariu2015-01-21-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | This patch configures and initializes the L2 switch on T1040QDS board. The L2 switch ports must be initialized according to the SerDes protocols. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
| * | board/T104xrdb: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYsCodrin Ciubotariu2015-01-21-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's T1040qds board may be configured to have up to 5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports, 2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2), connected to other two ports from an intergrated VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link ports have no PHYs attatched, so they don't have a corresponding MDIO. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/T1040qds: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYsCodrin Ciubotariu2015-01-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's T1040qds board may be configured to have up to 5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports, 2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2), connected to other two ports from an intergrated VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link ports have no PHYs attatched, so they don't have a corresponding MDIO. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/T1040qds: Fix lane-to-slot mapping for SerDes protocol 0x89Codrin Ciubotariu2015-01-21-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t1040qds: convert deep sleep to generic board interfacetang yuantian2015-01-16-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t102xqds: convert deep sleep to generic board interfacetang yuantian2015-01-16-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t1024rdb: Add support for T1024RDB-PBShengzhou Liu2015-01-16-4/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY. rcw_0x095 is used for 10G XFI + 3x PCIex1 rcw_0x135 is used for 2.5G SGMII + 2x PCIex1 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t102xrdb: convert deep sleep to generic board interfacetang yuantian2015-01-16-12/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Besides, added SPI/SD/NAND boot deep sleep support. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc: SECURE BOOT- Add secure boot target for T1042RDBgaurav rana2015-01-16-0/+1
| | | | | | | | | | | | | | | | | | | | | Secure boot target is added for T1042RDB platform. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t4240rdb: Add alternate SerDes 2 protocol to align with RCWChunhe Lan2015-01-16-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes 2 protocol 56 is not valid any longer due to the new RCW; protocol 55 is used instead, so add SerDes 2 protocol 55 to align with RCW. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-09 22:58:44 +0000