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* ENGR00171622 - FEC : workaround for Gb enet in sabrelite board.rel_imx_2.6.38_12.01.01imx_v2009.08_12.01.01Fugang Duan2012-01-11-3/+3
| | | | | | | | Micrel phy KSZ9021 Gb speed cannot work well in i.MX6 sabrelite board. Advertise phy is not 1000Base-T capable, and enet can work well at 100Mbps mode in 1000M environment(1G cable & 1G hub). Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00171115 add fec support in mx6q sabreauto boardHake Huang2011-12-31-36/+25
| | | | | | | | | | Add fec support for sabreauto board Need hardware rework: 1. Add R450 10.0k 2. Remove R1105 1k 3. short Pin 1,2 of u516, will impact CAN1 Signed-off-by: Hake Huang <b20222@freescale.com>
* ENGR00171008 MX6Q/MFGTOOL : disable the workaround for MFGTOOLHuang Shijie2011-12-28-7/+0
| | | | | | Disable the uboot workaround. It will crash the MFGTOOL. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00163697 - FEC : Adjust MX53 Network stream throughput.Fugang Duan2011-12-20-0/+550
| | | | | | | | | | | | | | | | | | | | | - When the system is very busy(such as play 1080p streaming in local) the WIFI & FEC performance were very low. - Enable the patch in uboot for WIFI and FEC performance: If WIFI connect to PORT2, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT2 If WIFI connect to port3, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT3 - The solution of the patch: I. Changing M4IF dynamic jump value to zero, which can guarantee FEC the high rate of accessing bus. II. Increase Master 4 priority for FEC. Increase Master 2 and AHBMAX priority for WIFI. - Test result: i.MX53 FEC bandwidth (1080p streaming playback in local): 47.1 Mbits/sec. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00170516 Enable the master mode for ENET PHY on MX6 SabreliteMahesh Mahadevan2011-12-16-2/+2
| | | | | | Fix the ENET PHY settings on MX6 Sabre-lite to enable Master mode Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00170405 Android: MX6Q_SL: Fix recovery key detectionZhang Jiejing2011-12-15-2/+1
| | | | | | | Fix recovery key detection, the VOL_DN key is low assert. Or it will always enter recovery mode. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00170299-2 Android:MX6Q_SL: add board support for recovery and fastboot.Zhang Jiejing2011-12-15-0/+175
| | | | | | | add mx6q sabrelite board support for fastboot and recovery. add recovery key check, same key as in MX53_SMD. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00169919 MX6Q ARM2 U-Boot : Support Pop CPU BoardEric Sun2011-12-13-3/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include - TEXT_BASE - RAM address and size - Initialization DCD - MMU related code Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is generated, set the board to serial download mode, use sb loader to run the bootloader. There is one line in the original DDR initialization script setmem /32 0x00B00000 = 0x1 however this address can not be accessed by DCD. A try to add it later in "dram_init" block the boot up. Waiting for IC team to give an explanation on it. Hold temperorily The MMU Change can be concluded as the following - Cacheable and Uncacheable SDRAM allocation changes to Phys Virtual Size Property ---------- ---------- -------- ---------- 0x10000000 0x10000000 256M cacheable 0x80000000 0x20000000 16M uncacheable 0x81000000 0x21000000 240M cacheable - TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start of SDRAM. This address makes sure that the text section of U-boot have the same Physical and Virtural address, thus the PC don't need to change when MMU is enabled. Also the text section is all allocated in cacheable memory, which may increase excecution performance. - Since this SDRAM allocation avoid overlap in physical memory between cacheable and uncacheable memory, the implementation of __ioremap can be ignored Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00169741 UBOOT : DDR3 initialization based on the MX6Q ARDPrabhu Sundararaj2011-12-12-384/+82
| | | | | | | Fix for DDR3 initialization based on the MX6Q ARD. This will reflect 2GB of RAM onboard. Signed-off-by: Prabhu Sundararaj <prabhu.sundararaj@freescale.com>
* ENGR00169655 pcba : merge i2c recovery patch to pcbaRobin Gong2011-12-09-0/+274
| | | | | | add i2c recovery function in board_lateinit,merge the patch of ENGR00163704 Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00169654 mx53_pcba: enable DDR auto-calibrationRobin Gong2011-12-07-178/+620
| | | | | | | Enabled the functioon of DDR auto-calibration in flash_header.S of HW PCBA. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00169500 mc34708 mx53_loco: 4s power off in QS boardRobin Gong2011-12-06-0/+1
| | | | | | Implement the power off function when push the PWR key for 4s Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00163704: MX5X: add i2c recovery function in board_lateinit.Zhang Jiejing2011-12-05-0/+530
| | | | | | | | | | | | | | | | | | This patch add a i2c bus recovery function, the i2c bus busy because some device pull down the I2C SDA line. This happens when Host is reading some byte from slave, and then host is reset/reboot. Since in this case, device is controlling i2c SDA line, the only thing host can do this give the clock on SCL and sending NAK, and STOP to finish this transaction. To fix this issue: when we found SDA is low, we generate 8 clock to let device send data, then send a NAK, and STOP to finish this I2C transaction , after this the clock will be clean. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00163370 Android: uboot: mx53_smd fix warnning messageZhang Jiejing2011-11-29-2/+2
| | | | | | Fix minor error when adding recovery related code. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00163239-2 mc34708: enable extra charging circuitRobby Cai2011-11-28-0/+11
| | | | | | | | | current schema is to enable this extra charging circuit, and then enable or disable it by checking VBatt is less or more than 3.4v. If VBatt is less than 3.4v, enable it; otherwise disable it. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00163239-1 mc34708: fix not charging issue in ubootRobby Cai2011-11-28-3/+13
| | | | | | there's some incorrect setting in spi mode, fixed in this patch. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00162717 mx53_smd/mx53_loco DA9053: reset da9053 i2c and add dummy writeWayne Zou2011-11-25-66/+164
| | | | | | | | mx53_smd, mx53_loco DA9053: reset da9053 i2c by sending 9 dummy clock and start/stop when bootup and add dummy write when accessing da9053 registers. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00162709 Add Support for MX6Q Sabre AutoEric Sun2011-11-21-0/+1846
| | | | | | | 1. Change RAM size from 2GB to 1GB 2. Default boot from MMC Dev 2 Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00162491 Android: MX53_SMD: enter recovery mode by key.Zhang Jiejing2011-11-18-1/+16
| | | | | | | | | | | Implement a key press check on recovery mode check. User can press Vol- key to enter recovery mode when boot. Idealy, should be a combo key press together, but on SMD it only can Vol+ or Vol- but it can't press together. More usuful for user and less bug. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00162437 uboot mc34708 pcba : add spi support on mc34708Robin Gong2011-11-17-8/+134
| | | | | | | | Rev C of pcba will connect mc34708 by spi default, so uboot should support it: 1. add spi support in mx53_pcba 2. move pmic voltage config from board_init to board_late_init 3. support both I2C and SPI on mc34708 in one image Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00155891 : Fix reboot stress test failed issueRobin Gong2011-11-16-258/+371
| | | | | | | | | | | | | | If we replace DCD mode with plug-in mode in u-boot , we found DDR not stable. We should enable "Force Measurement" after the delay line parameters is configured in the plug-in code, for example: 0x63fd9088 = 0x34333936 0x63fd9090 = 0x49434942 0x63fd90F8 = 0x00000800 "Force Measurement" update all of mx53 DDR script, include mx53_smd,mx53_loco,mx53_evk,mx53_ard, mx53_pcba, at the same time, mx53_pcba will change from DCD mode to plug-in mode in flash_header.S Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00161852: remove u-boot build warnings for mx6qTerry Lv2011-11-10-1/+3
| | | | | | Remove u-boot build warnings for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00161846 uboot mx6q_arm2: adjust IPU axi-id0/1 Qos valueJason Chen2011-11-10-6/+6
| | | | | | | | | set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7, mx6q use AXI-id0 for IPU display channel, it should has highest priority(bypass), and AXI-id1 for other IPU channel, it has high priority. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00161354 MX6Q ARM2 U_BOOT: "mmc dev 0" or "mmc dev 1" cmds will hangAnish Trivedi2011-11-04-6/+10
| | | | | | | | Ungate the clocks to SD1 and SD2 ports (on baseboard of ARM2 system) so that the above cmds do not hang waiting for cmd to complete or timeout. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00161415: mc34708: set 1p5Robby Cai2011-11-04-2/+2
| | | | | | set charging current limit to 1p5 Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00157106 uboot mx6q: adjust IPU axi-id0/1 Qos valueJason Chen2011-11-04-3/+3
| | | | | | | | | set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7, mx6q use AXI-id0 for IPU display channel, it should has highest priority(bypass), and AXI-id1 for other IPU channel, it has high priority. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00161317 - MX6Q: Integrate plugin and dcd DRAM init script in uboot.Fugang Duan2011-11-04-0/+300
| | | | | | | | | - Add plugin DRAM init script in flash_header.S file. - Define CONFIG_FLASH_PLUG_IN in mx6q_sabreauto.h to switch plugin mode. - DDR support 528MHz and 480MHz in plugin mode. Switch DDR clock to 480M according to define CONFIG_IPG_40M_FR_PLL3. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00161373 Move the MAC address read from fuse code to MX6 SoC fileMahesh Mahadevan2011-11-03-57/+0
| | | | | | | Move the code to read the mac address from the fuse to SoC file and out of the board file Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161254 MX6Q: Add NAND support in UbootAllen Xu2011-11-03-0/+56
| | | | | | | | Add iomux and clock setting in Uboot code to support NAND, due to the conflict between NAND and SD, NAND function is not enabled in default configuration. Signed-off-by: Allen Xu <allen.xu@freescale.com>
* ENGR00161294 Update MX6 code to read MAC address from fusesMahesh Mahadevan2011-11-02-9/+20
| | | | | | Fix the code to read the MAC address correctly from the fuses Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161133: Add spi-nor support for mx6qTerry Lv2011-11-01-0/+68
| | | | | | Add spi-nor support for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00161004 MX6Q Uboot Rename sabreauto to arm2 boardAnish Trivedi2011-10-28-10/+14
| | | | | | | | | Sabreauto is an inaccurate name for the Armadillo2 board that this code is actually meant for. So, replaced "sabreauto" in folder names, file names, configs, and code with "arm2". Created a new machine id for ARM2 board. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139221 USDHC Add SDXC UHS-I supportAnish Trivedi2011-10-27-4/+9
| | | | | | | Modified MMC library for UHS-I command sequence Added support to USDHC driver for UHS-I Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00160514: clean up compiler warning for mx6qTerry Lv2011-10-26-2/+3
| | | | | | Clean up compiler warning. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00160399 Added support for the MX6Q Sabre-lite boardMahesh Mahadevan2011-10-25-6/+1140
| | | | | | Includes support for uSDHC read, write, FEC, SPI-NOR etc. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00156934: Update mx35 AIPS max dbg m3if esdctl settingsTerry Lv2011-10-18-18/+32
| | | | | | | This patch is to fix mx35 TVIN flicker issue. It will change AIPS, M3IF, MAX, DBG and esdctl settings. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00156930: Update MX35 DDR2 scriptsTerry Lv2011-10-18-69/+414
| | | | | | | | | | Update MX35 DDR2 scripts for that when enabling 256MB, the CSD1 is not stable. 1. Add CSD1 configs to support 256M RAM. 2. Add mx35 TO2 256M RAM configs. 3. Update DDR init code in lowlevel_init.S for external boot. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139279-3 MX6Q: invalidate the D-CACHEHuang Shijie2011-10-14-0/+37
| | | | | | | | | | | The USB boot mode does not invalidate the D-CACHE, so the uboot will DEAD when it tries to invalidate the random data in the cache line. The MMC boot will do the MMU init which will do the D-CACHE invalidation. So the MMC boot will ok in the boot procedure. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00159845 [MX6]lpddr2 board, put MMDC into power saving modeAnson Huang2011-10-13-2/+10
| | | | | | | | For lpddr2 board. 1. Put mmdc into power saving mode; 2. Do the necessary setting for AXI cache and IPU Qos. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00159696 [MX6]Enable lpddr2 boardAnson Huang2011-10-11-0/+169
| | | | | | | And new config to enable lpddr2 board with H9TKNNN4KDMPQR-NDM chip. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00158184 mx53 smd: use highest value for unknown board revision valueWayne Zou2011-09-26-1/+4
| | | | | | mx53 smd: use highest value for unknown board revision value Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00157538 remove VDIG_PLL setting in plug-in codeLily Zhang2011-09-23-20/+0
| | | | | | | | According to the datasheet, VDIG_PLL needs to be increased to 1.3v for TO2.0. This operation has been done in the low_level_init.S. Remove the duplicated code here. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00155569 mc34708: change global reset time as 4s of LOCO and PCBARobin Gong2011-09-19-0/+22
| | | | | | reduce the time of global reset to 4s in the boards of loco and pcba Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00156389: turn off child clocks before reconfigure perclk_rootTerry Lv2011-09-13-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. Certain steps are required to reconfigure perclk_root. If don't follow these steps, GPT timer may stop and the kernel stops at " "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00156098 mx53_smd/mx53_loco: DA9053 I2C SDA stuck low issue on bootupWayne Zou2011-09-06-2/+204
| | | | | | | | | | | | | | | | For DA9053 I2C SDA stuck low issue: the I2C block in DA9053 may not correctly receive a Power On Reset and device is in unknown state during start-up. The only way to get the chip into known state before any communication with the Chip via I2C is to dummy clock the I2C and bring it in a state where I2C can communicate. Dialog suggested to provide 9 clock on SCL. Dialog don't know the exact reason for the fault and assume it is because some random noise or spurious behaviour. This has to been done in host platform specific I2C driver during start-up when the I2C is being configured at platform level to supply with dummy 9 clock on SCL. Dialog I2C driver has no control to provide dummy 9 clock on SCL. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-2/+275
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHzTerry Lv2011-09-01-6/+42
| | | | | | | | 1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155279: Change ESDCTL_0x82228080 to ESDCTL_0x82226080 for mx35Terry Lv2011-09-01-3/+4
| | | | | | | | | | In mx35, when testing TVIN, the screen will flick. We find that flickers will get better when using ESDCTL_0x82226080 against ESDCTL_0x82228080 for register SCDCTL0. The origin value ESDCTL_0x82228080 in lowlevel_init.S will be called in external boot which will reduce the bandwidth. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155739: mx53 evk mmu wrong mapped two csd slotsTerry Lv2011-09-01-10/+4
| | | | | | | mx53 evk mmu wrong mapped two csd slots. Actually evk only has one slot. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154666-2: Align u-boot mmc command with communityTerry Lv2011-09-01-5/+5
| | | | | | Trivial change to remove build warnings. Signed-off-by: Terry Lv <r65388@freescale.com>
generated by cgit v1.1 at 2024-12-04 14:16:28 +0000