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* Enabled the Freescale SGMII riser card on 8536DSJason Jin2008-10-18-0/+42
| | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* Enabled the Freescale SGMII riser card on 8572DSLiu Yu2008-10-18-0/+48
| | | | | | | This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* Make pixis_set_sgmii more general to support MPC85xx boards.Liu Yu2008-10-18-3/+19
| | | | | | | | | | | | The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* mpc8572 additional end-point modeEd Swarthout2008-10-18-2/+2
| | | | | | | | | | | mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0. Include host_agent == 0 decode for end-point determination. This is not needed for the ds reference board since pcie3 will be a host in order to connect to the uli chip. Include it here as a reference for other mpc8572 boards. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* pixis do not print long help if not configuredEd Swarthout2008-10-18-0/+4
| | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* Add DDR options setting on MPC8641HPCN boardHaiying Wang2008-10-18-36/+110
| | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-28/+94
| | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-11/+44
| | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xx: Improve flash remapping on MPC8572DS & MPC8536DSKumar Gala2008-10-18-14/+10
| | | | | | | | Changing the flash from cacheable to cache-inhibited was taking a significant amount of time due to the fact that we were iterating over the full 256M of flash. Instead we can just flush the L1 d-cache and invalidate the i-cache. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-1573/+1573
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Fix compiler warning in lib_ppc/board.cHeiko Schocher2008-10-15-1/+1
| | | | | | | Fix compiler warning introduced by commit 0f8cbc18 Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Do not init SATA when disabled on 8536DS.Jason Jin2008-10-14-0/+12
| | | | | | | | | | SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the driver still try to access the SATA registers, the cpu will hangup. This patch try to fix this by reading the serdes status before the SATA initialize. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl_diu: fix alignment error that caused malloc corruptionNikita V. Youshchenko2008-10-14-3/+3
| | | | | | | | | | | | | | | | | | | When aligning malloc()ed screen_base, invalid offset was added. This not only caused misaligned result (which did not cause hardware misbehaviour), but - worse - caused screen_base + smem_len to be out of malloc()ed space, which in turn caused breakage of futher malloc()/free() operation. This patch fixes screen_base alignment. Also this patch makes memset() that cleans framebuffer to be executed on first initialization of diu, not only on re-initialization. It looks correct to clean the framebuffer instead of displaying random garbage; I believe that was disabled only because that memset caused breakage of malloc/free described above - which no longer happens with the fix described above. Signed-off-by: Nikita V. Youshchenko <yoush@debian.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-12-1/+1
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| * FSL: Fix get_cpu_board_revision() return value.Rafal Czubak2008-10-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | get_cpu_board_revision() returned board revision based on information stored in global static struct eeprom. It should instead use one from local struct board_eeprom, to which the data is actually read from EEPROM. The bug led to system hang after printing L1 cache information on U-Boot startup. The problem was observed on MPC8555CDS system and possibly affects other Freescale MPC85xx boards using CFG_I2C_EEPROM_CCID. The change has been successfully tested on MPC8555CDS system. Signed-off-by: Rafal Czubak <rcz@semihalf.com>
* | mpc83xx: spd_sdram: fix ddr sdram base address assignment bugAnton Vorontsov2008-09-24-6/+6
|/ | | | | | | | | | | The spd_dram code shifts the base address, then masks 20 bits, but forgets to shift the base address back. Fix this by just masking the base address correctly. Found this bug while trying to relocate a DDR memory at the base != 0. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-10/+10
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-3/+3
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename environment.c in env_embedded.c to reflect is functionalityJean-Christophe PLAGNIOL-VILLARD2008-09-10-21/+21
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Update Freescale 85xx boards to sys_eeprom.cTimur Tabi2008-09-09-61/+0
| | | | | | | | | The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID format, and so it obsoletes board/freescale/common/cds_eeprom.c. Freescale 86xx boards already use sys_eeprom.c, so this patch migrates the remaining Freescale 85xx boards to use it as well. cds_eeprom.c is deleted. Signed-off-by: Timur Tabi <timur@freescale.com>
* Moved initialization of EEPRO100 Ethernet controller to board_eth_init()Ben Warren2008-09-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards: db64360 db64460 katmai taihu taishan yucca cpc45 cpu87 eXalion elppc debris kvme080 mpc8315erdb integratorap ixdp425 oxc pm826 pm828 pm854 pm856 ppmc7xx sc3 sc520_spunk sorcery tqm8272 tqm85xx utx8245 Removed initialization of the driver from net/eth.c Also, wrapped contents of pci_eth_init() by CONFIG_PCI. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Moved initialization of TSI108 Ethernet controller to board_eth_init()Ben Warren2008-09-02-0/+10
| | | | | | | | | Affected boards: mpc7448hpc2 Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Moved initialization of RTL8139 Ethernet controller to board_eth_init()Ben Warren2008-09-02-4/+12
| | | | | | | | | | | | | Affected boards: hidden_dragon MPC8544DS MPC8610HPCN R2DPLUS TB0229 Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Introduce netdev.h header file and remove externsBen Warren2008-09-02-6/+2
| | | | | | | This addresses all drivers whose initializers have already been moved to board_eth_init()/cpu_eth_init(). Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Add pixis_set_sgmii commandAndy Fleming2008-09-02-0/+55
| | | | | | | | | | | | | | | | | | The 8544DS and 8572DS platforms support an optional SGMII riser card to expose ethernet over an SGMII interface. Once the card is in, it is also necessary to configure the board such that it uses the card, rather than the on-board ethernet ports. This can either be done by flipping dip switches on the motherboard, or by modifying registers in the pixis. Either way requires a reboot. This adds a command to allow users to choose which ports are routed through the SGMII card, and which through the onboard ports. It also allows users to revert to the current switch settings. This code does not work on the 8572, as the PIXIS is different. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Add SGMII support for the 8544 DSAndy Fleming2008-09-02-0/+39
| | | | | | | | | The 8544 DS has an optional SGMII Riser card, which uses different PHY addresses. Check if we are in SGMII mode, and invoke the SGMII Riser setup code if so. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Add support for Freescale SGMII Riser CardAndy Fleming2008-09-02-0/+42
| | | | | | | | | | | The 8544DS and 8572DS systems have an optional SGMII riser card which exposes new ethernet ports which are connected to the eTSECs via an SGMII interface. The SGMII PHYs for this board are offset from the standard PHY addresses, so this code modifies the passed in tsec_info structure to use the SGMII PHYs on the card, instead. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* ColdFire: Multiple fixes for MCF5445x platformsTsiChung Liew2008-08-28-6/+9
| | | | | | | | | | Add FEC pin set and mii reset in __mii_init(). Change legacy flash vendor from 2 to AMD LEGACY (0xFFF0), change cfi_offset to 0, and change CFG_FLASH_CFI to CONFIG_FLASH_CFI_LEGACY. Correct M54451EVB and M54455EVB env settings in configuration file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-08-28-34/+2711
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| * mpc85xx: Add support for the MPC8536DS reference boardKumar Gala2008-08-27-0/+1077
| | | | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-0/+1011
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * FSL DDR: Convert MPC8544DS to new DDR code.Kumar Gala2008-08-27-7/+93
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * FSL DDR: Convert MPC8568MDS to new DDR code.Jon Loeliger2008-08-27-6/+97
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * FSL DDR: Convert MPC8548CDS to new DDR code.Jon Loeliger2008-08-27-1/+88
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * FSL DDR: Convert MPC8541CDS to new DDR code.Jon Loeliger2008-08-27-1/+85
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * FSL DDR: Convert MPC8555ADS to new DDR code.Jon Loeliger2008-08-27-1/+87
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * FSL DDR: Convert MPC8560ADS to new DDR code.Jon Loeliger2008-08-27-8/+86
| | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * FSL DDR: Convert MPC8540ADS to new DDR code.Kumar Gala2008-08-27-10/+87
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Moved initialization of ULI526X Ethernet driver to board code.Ben Warren2008-08-26-0/+10
|/ | | | | | | The only board using this driver is the Freescale MPC8610HPCD board. Removed initialization for the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* FSL DDR: Convert MPC8610HPCD to new DDR code.Jon Loeliger2008-08-27-6/+86
| | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Convert MPC8641HPCN to new DDR code.Kumar Gala2008-08-27-7/+95
| | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc7448hpc2: Fix PCI I/O space mapping.Randy Vinson2008-08-26-2/+2
| | | | | | | | | | PCI I/O space is currently mapped 1:1 at 0xFA000000. Linux requires PCI I/O space to start at 0 on the PCI bus. This patch maps PCI I/O space such that 0xFA000000 in the processor's address space maps to 0 on the PCI I/O bus. Signed-off-by Randy Vinson <rvinson@mvista.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
* MPC8349EMDS: Add PCI Agent (PCISLAVE) supportIra W. Snyder2008-08-25-0/+58
| | | | | | | | Add the ability for the MPC8349EMDS to run in PCI Agent mode, acting as a PCI card rather than a host computer. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC8349EMDS: use 83XX_GENERIC_PCI setup codeIra W. Snyder2008-08-25-317/+60
| | | | | | | | Change the MPC8349EMDS board to use the generic PCI initialization code for the mpc83xx cpu. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'next'Kim Phillips2008-08-25-2/+37
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| * 83xx: mpc8315erdb: fix silly thinko in fdt_tsec1_fixupAnton Vorontsov2008-07-16-9/+10
| | | | | | | | | | | | | | | | | | | | The thinko was quite silly indeed, I messed with !ptr. Normally this would trigger some fault, but in U-Boot NULL pointer is equal to phys 0, so the code was working still, just didn't actually test mpc8315erdb environment variable value. Heh. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * 83xx: mpc8315erdb: add support for switching between ULPI/UTMI USB PHYsAnton Vorontsov2008-07-16-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale ships MPC8315E-RDB boards either with TSEC1 and USB UTMI support, or without TSEC1 but with USB ULPI PHY support in addition. With this patch user can specify desired USB PHY. Also, it seems that we can't distinguish the two boards in software, so user have to set `mpc8315erdb' environment variable to either 'tsec1' (TSEC1 enabled) or `ulpi' (board with ULPI PHY, TSEC1 disabled), so that Linux will not probe for TSEC1. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Clean up usage of icache_disable/dcache_disableKumar Gala2008-08-19-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | There is no point in disabling the icache on 7xx/74xx/86xx parts and not also flushing the icache. All callers of invalidate_l1_instruction_cache() call icache_disable() right after. Make it so icache_disable() calls invalidate_l1_instruction_cache() for us. Also, dcache_disable() already calls dcache_flush() so there is no point in the explicit calls of dcache_flush(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ColdFire: Multiple fixes for M5282EVBTsiChung Liew2008-08-14-2/+8
| | | | | | | | | | | | | | | | | | Incorrect CFG_HZ value, change 1000000 to 1000. Rename #waring to #warning. RAMBAR1 uses twice in start.S, rename the later to FLASHBAR. Insert nop for DRAM setup. And, env_offset in linker file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | ColdFire: Move m5282evb from board to board/freescaleTsiChung Liew2008-08-14-0/+608
| | | | | | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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