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* ENGR00179150 MX6Q_ARM2 HAB Boot : avoid uImage authentication on un-fused chipEric Sun2012-04-09-23/+81
| | | | | | | | | Before running authentication on uImage in DDR, u-boot first check if SEC_CONFIG[1] (OTP_CFG5[1]) is burned. If so, it means the chip is in secure configuration, the authentication continues; if not, the chip in not in secure configuration, just bypass the authentication Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176537 mx6qsabreauto: i2c3_sda route settingAdrian Alonso2012-04-05-2/+24
| | | | | | | | | | * In RevB boards a steer logic circuit enables the route path of I2C3_SDA signal and is controlled by EIM_A24__GPIO_5_4 pad. * Configure GPIO_5_4 as as output and enable steer logic circuit. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00139223-1 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 1)Eric Sun2012-04-01-2/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first stage of High Assurance Boot (HAB) is the authentication of U-boot. A CST tool is used to generate the CSF data, which include public key, certificate and instruction of authentication process. Then it is attached to the original u-boot.bin The IVT should be modified to contain a pointer to the CSF data. The original u-boot.bin is with size between 0x27000 to 0x28000. For convinence, we first extend the u-boot.bin to 0x2F000 (with fill 0xFF). Then concatenate it with the CSF data. The combined image is again extend to a fixed length (0x31000), which is used as the IVT size parameter. The new memory layout is as the following. U-Boot Image +-------------+ | Blank | |-------------| 0x400 | IVT |-----------------------+ |-------------| | | | | | | | | | | |Remaining UB | | CSF pointer | | | | | | | | | |-------------| | | | | | Fill Data | | | | | |-------------| 0x2F000 <-------------+ | | | CSF Data | | | |-------------| | | | Fill Data | | | +-------------+ 0x31000 HAB APIs are ROM implemented, the entry table is located in a fixed location in the ROM. We export them so that during the HAB we can have some information about the secure boot process. For convinience some wrapper API is implemented based on the HAB APIs. - get_hab_status : used to dump information of authentication result - authenticate_image : used by u-boot to authenticate uImage For security hardware to function, CAAM related clock (CG0[4~6]) must be open. They are default closed in the original U-boot. "hab_caam_clock_enable" and "hab_caam_clock_disable" are created to open and close these clock gates. The generation of CSF data is not in the scope of this patch. CST tool will be used for this purpose. The procedure will be introduced in another document. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176834-4 - [imx]:add macro define to include chip head fileFugang Duan2012-03-31-1/+3
| | | | | | | - Different chip will include different head file, so add macro define to limit the use range. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00178558 mx6solo sabreauto: integrate DDR3 script V1.1Lily Zhang2012-03-30-95/+99
| | | | | | | | | This patch is used to integrate DDR3 script V1.1 of mx6solo sabreauto MX6DL_init_DDR3_400MHZ_32bit_sabre_1_1.inc under http://compass.freescale.net/livelink/livelink?func=ll&objid =225128962&objAction=browse&sort=name Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00177954 mx6solo sabreauto: remove MMDC1 settingrel_imx_3.0.15_12.03.00Lily Zhang2012-03-26-44/+39
| | | | | | | Remove MMDC1 setting from DDR script of mx6solo sabreauto if it's not used. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00177783: i.mx6dl: sabresd revB: update DD3 init scriptJason Liu2012-03-23-38/+41
| | | | | | | | | Update the DDR3 script on i.mx6dl SabreSD revB board, the script got from: http://wiki.freescale.net/download/attachments/33954617/MX6DL_init_DDR3 _400MHz_64bit_1_2_For_SD_RevB.inc?version=1&modificationDate=1332495827000 Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00176837-2 - imx6 sabreauto : add i2c3 support for revb board.Fugang Duan2012-03-22-4/+8
| | | | | | - Add i2c3_SDA iomux config for the change of signal traces. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176837-1 - imx6 sabreauto : add net support for revb boards.Fugang Duan2012-03-22-11/+28
| | | | | | | - In imx6 sabreauto board REVB Ethernet phy adopt AR8031. Add phy init rework. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00177244 - imx6 : Use common fsl_sys_rev to check board reversionFugang Duan2012-03-20-54/+7
| | | | | | | | | - Use fsl_sys_rev to check Sebreauto board reversion. - Add macro define for expedient print the board and chip name. mx6_chip_name() mx6_board_rev_name() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-3 - i.MX6DL sabresd : DDR init script updateFugang Duan2012-03-20-10/+10
| | | | | | | | | | | Use the ddr init script “MX6DL_init_DDR3_400MHz_64bit_1.2.inc” for SD revB with Rigel mounted, and update the calibration parameters (write leveling, DQS gating, read delay, write delay), which is located at: http://compass.freescale.net/livelink/livelink?func=ll& objid=225128962&objAction=browse&sort=name Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-2 - i.MX6DL sabresd: board bringupFugang Duan2012-03-20-24/+299
| | | | | | | | | | | | | The serial of patches adds the initial support for mx6dl sabra sd board: - DDR3 400MHz@64bit, 1G, 256M*4 - SD/MMC basic operations - Add PIN/IOMUX support for mmx6dl sabresd. - Ethernet is ok for 100/1000Mbps. - OTP fuse Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-1 - [imx6] : add fsl_system_rev to check chip and board.Fugang Duan2012-03-20-0/+116
| | | | | | | | | | | | | | | - Add fsl_system_rev to distinguish chip ID and board reversion. - Add some api: mx6_chip_is_dq() mx6_chip_is_dl() mx6_chip_is_solo() mx6_chip_is_sololite() mx6_board_is_reva() mx6_board_is_revb() mx6_board_is_revc() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176347-9 fec : increase wait time for phy linkFugang Duan2012-03-13-17/+0
| | | | | | | | | | | | | | - remove the excrescent code in enet_board_init function. - KSZ9021 phy auto-negotiation in mx6solo sabreauto RevA is used to establish link with the remote hub or switch. In general, the negotiation time is about 3-5 senconds But connecting to Gbps hub, the time is range from 8s to 15s. So, changing the MAX link waiting time to 20s. According to repetitious tests, solo ARD ethernet is ok in 100Mbps environment. It is not stable in 1000Mbps mode. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176347-6 mx6solo sabreauto: remove build warningLily Zhang2012-03-13-2/+5
| | | | | | | | | | Remove the following build warning: mx6q_sabreauto.c: In function 'enet_board_init': mx6q_sabreauto.c:999: warning: unused variable 'reg' mx6q_sabreauto.c: At top level: mx6q_sabreauto.c:921: warning: 'phy_read' defined but not used Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-5 mx6solo sabreauto: set system_revLily Zhang2012-03-13-11/+55
| | | | | | | | | | | | | | | | | Add set_system_rev function. The layout of system_rev is: bit 0-7: Chip Revision ID. Read from Anatop register bit 8-11: Board Revision ID. Read from fuse OCOTP_GP1[15:8] 1: RevA Board 0: RevB board, Unknown board bit 12-19: Chip Silicon ID. Read from Anatop register 0x63: i.MX 6Dual/Quad 0x61: i.MX 6Solo/DualLite board_is_rev(system_rev,BOARD_REV_1) can be used to distinguish RevB board. board_is_rev(system_rev,BOARD_REV_2) is for RevA board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-3 mx6solo sabreauto: add board supportLily Zhang2012-03-13-28/+162
| | | | | | | | - Add PIN/IOMUX support for mx6solo sabreauto board - Remove GPIO_9 codes because GPIO_9 is not the backlight - change system_rev as 0x610000 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-2 mx6solo sabreauto: add DDR3 supportLily Zhang2012-03-13-2/+109
| | | | | | | | Add DDR3 script (400MHz@32 bit) in mx6solo sabre auto board. MX6Solo_DDR3_400MHZ_32bit.inc was delivered on Mar 7, 2012 by Fan Chongbin-B32609 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176235 mx6 ARD: Add splash screen supportLily Zhang2012-03-06-6/+6
| | | | | | | | | | | | | | | | | | | This patch adds splash screen support for MX6 ARD. Changes: - Configure GPIO_3 as I2C3_SCL - Change MAX7310 I2C address as 0x30 - Enable LVDS power Usage: 1. To enable splash screen by default, define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2. Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176186 mx6dq ARD: add MFG tool supportLily Zhang2012-03-06-8/+1
| | | | | | Add MFG tool support for i.MX6DQ ARD board Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00175981-1 mx53 smd: add CPU 1.2GHz configurationLily Zhang2012-03-02-1/+12
| | | | | | | | | CONFIG_CPU_1_2G is used to enable 1.2GHz@1.3V. To enable 1.2GHz by default, enable CONFIG_CPU_1_2G into config file. For example, uncomment CONFIG_CPU_1_2G in mx53_smd.h or mx53_smd_android.h. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00175117 [MX6DL LPDDR2 Board] Apply Initializtion script and enable U-BootEric Sun2012-02-29-1/+306
| | | | | | | | | | | | | | | | | Apply script "Mx6DL_init_LPDDR2_400MHz_Micron_1.1.inc" in IVT, make U-boot work for the LPDDR2 Board. The Make target name for the new board is "MX6DL_ARM2_LPDDR2_CONFIG" The script is provided by Chen Wei - B26879 for a quick bring up, which don't have a corresponding compass link. It is uploaded to CR ticket page for reference. Originally for MX6DL DDR3 board, "CONFIG_MX6DL" is defined. It is used by "board/freescale/mx6q_arm2/flash_header.S" to select the correct IVT. Since MX6DL LPDDR2 board also define this macro, for distiguish purpose, another 2 macros "CONFIG_MX6DL_DDR3", "CONFIG_MX6DL_LDPPR2" are defined Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00175091 MX6Q_SABRESD: android: add recovery checkZhang Jiejing2012-02-27-39/+37
| | | | | | | | define a new macro to show which mmc bus was main storage in recovery check, only check the main storage /cache partition. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00174536-1 booti: add booti command support.Zhang Jiejing2012-02-27-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support booti command which can boot from a boot.img boot.img is a zImage + ramdisk.img + bootargs + boot addr which include these info can be used to avoid mis match between kernel and ramdisk, also can avoid commit to chagne default bootargs. For example: > booti mmc1 command will read the boot.img from 1M offset, and then parser the bootargs and ramdisk then do the boot from that zImage. > booti mmc1 recovery will going to read the recovery's partition no and offset and boot from recovery image. this recovery image also a zImage + ramdisk bootargs: if uboot have define a env var 'bootargs', booti command will use this bootargs as kernel cmdline if you want use boot.img 's bootargs, just type: > setenv bootargs in uboot to clear the bootargs in uboot env. our default uboot env will be NULL in config file. also, android use boot.img to support OTA. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00174326 MX6Q_SABRESD: add android related function and config.Zhang Jiejing2012-02-15-0/+162
| | | | | | | | | | enable mfg profile. enable recovery mode. mx6q_sabresd board's usb otg have HW issue, disable it in android profile. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00174104-1: Add conditional CONFIG to fix build breakTerry Lv2012-02-13-0/+9
| | | | | | | | | | | Add CONFIG_MXC_FEC macro to fec init code. Add CONFIG_VIDEO_MX5 to ipu init code. Change temperature function as static. For in iram boot, FEC configs is not needed, those FEC init code will cause build errors. These changes can reduce image size. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00174155: i.mx6sdl: add 32bit DDR support on ARM2 boardJason Liu2012-02-09-0/+5
| | | | | | | | | | | The 32bit DDR script got from the following link: http://compass.freescale.net/livelink/livelink/225194568/ MX6DL_init_DDR3_400MHZ_32bit_1.0.inc.txt?func=doc.Fetch&nodeid=225194568 The DDR hw connection on the ARM2 board is 64bit wire, but we can make it use as 32bit, the side effect is that DDR access size will reduce to the half Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00174055: i.mx6dl: ddr: update ddr script to 400M_64bit_v1.1Jason Liu2012-02-09-14/+14
| | | | | | | | | The script we get from the following link: http://compass.freescale.net/livelink/livelink/225193471/MX6DL_init_ DDR3_400MHz_64bit_1.1.inc.txt?func=doc.Fetch&nodeid=225193471 Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00173966-4: ARM2: add initial support for i.mx6sdlJason Liu2012-02-07-26/+170
| | | | | | | | | | | | | | | | | This patch add the initial support for i.mx6dl ARM2 board -SD/MMC basic -DDR 400Mhz, -FEC,basic Due to i.mx6dl shares the same board with i.mx6q on ARM2, the most common code should be the same as the i.mx6q ARM2 So, no need to create one seperate board file for i.mx6dl. But We can't simply resue anything from the board file since the i.mx6dl iomux is changed and thus we have to deal with the difference between i.mx6q and i.mx6dl for the pad setting part. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00173966-3: ARM2: i.mx6dl: add the DDR scriptJason Liu2012-02-07-3/+133
| | | | | | | | | integrate DDR script http://compass.freescale.net/livelink/ livelink/225147268/rigel_temp.inc.txt?func=doc.Fetch &nodeid=225147268 Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00172343 Add suport for i.MX 6Q Sabre Smart DeviceNancy Chen2012-01-24-0/+1370
| | | | | | | | Add suport for i.MX 6Quad SABRE Smart Device. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com> Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
* ENGR00171622 - FEC : workaround for Gb enet in sabrelite board.Fugang Duan2012-01-11-3/+3
| | | | | | | | Micrel phy KSZ9021 Gb speed cannot work well in i.MX6 sabrelite board. Advertise phy is not 1000Base-T capable, and enet can work well at 100Mbps mode in 1000M environment(1G cable & 1G hub). Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00171115 add fec support in mx6q sabreauto boardHake Huang2011-12-31-36/+25
| | | | | | | | | | Add fec support for sabreauto board Need hardware rework: 1. Add R450 10.0k 2. Remove R1105 1k 3. short Pin 1,2 of u516, will impact CAN1 Signed-off-by: Hake Huang <b20222@freescale.com>
* ENGR00171008 MX6Q/MFGTOOL : disable the workaround for MFGTOOLHuang Shijie2011-12-28-7/+0
| | | | | | Disable the uboot workaround. It will crash the MFGTOOL. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00163697 - FEC : Adjust MX53 Network stream throughput.Fugang Duan2011-12-20-0/+550
| | | | | | | | | | | | | | | | | | | | | - When the system is very busy(such as play 1080p streaming in local) the WIFI & FEC performance were very low. - Enable the patch in uboot for WIFI and FEC performance: If WIFI connect to PORT2, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT2 If WIFI connect to port3, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT3 - The solution of the patch: I. Changing M4IF dynamic jump value to zero, which can guarantee FEC the high rate of accessing bus. II. Increase Master 4 priority for FEC. Increase Master 2 and AHBMAX priority for WIFI. - Test result: i.MX53 FEC bandwidth (1080p streaming playback in local): 47.1 Mbits/sec. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00170516 Enable the master mode for ENET PHY on MX6 SabreliteMahesh Mahadevan2011-12-16-2/+2
| | | | | | Fix the ENET PHY settings on MX6 Sabre-lite to enable Master mode Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00170405 Android: MX6Q_SL: Fix recovery key detectionZhang Jiejing2011-12-15-2/+1
| | | | | | | Fix recovery key detection, the VOL_DN key is low assert. Or it will always enter recovery mode. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00170299-2 Android:MX6Q_SL: add board support for recovery and fastboot.Zhang Jiejing2011-12-15-0/+175
| | | | | | | add mx6q sabrelite board support for fastboot and recovery. add recovery key check, same key as in MX53_SMD. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00169919 MX6Q ARM2 U-Boot : Support Pop CPU BoardEric Sun2011-12-13-3/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include - TEXT_BASE - RAM address and size - Initialization DCD - MMU related code Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is generated, set the board to serial download mode, use sb loader to run the bootloader. There is one line in the original DDR initialization script setmem /32 0x00B00000 = 0x1 however this address can not be accessed by DCD. A try to add it later in "dram_init" block the boot up. Waiting for IC team to give an explanation on it. Hold temperorily The MMU Change can be concluded as the following - Cacheable and Uncacheable SDRAM allocation changes to Phys Virtual Size Property ---------- ---------- -------- ---------- 0x10000000 0x10000000 256M cacheable 0x80000000 0x20000000 16M uncacheable 0x81000000 0x21000000 240M cacheable - TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start of SDRAM. This address makes sure that the text section of U-boot have the same Physical and Virtural address, thus the PC don't need to change when MMU is enabled. Also the text section is all allocated in cacheable memory, which may increase excecution performance. - Since this SDRAM allocation avoid overlap in physical memory between cacheable and uncacheable memory, the implementation of __ioremap can be ignored Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00169741 UBOOT : DDR3 initialization based on the MX6Q ARDPrabhu Sundararaj2011-12-12-384/+82
| | | | | | | Fix for DDR3 initialization based on the MX6Q ARD. This will reflect 2GB of RAM onboard. Signed-off-by: Prabhu Sundararaj <prabhu.sundararaj@freescale.com>
* ENGR00169655 pcba : merge i2c recovery patch to pcbaRobin Gong2011-12-09-0/+274
| | | | | | add i2c recovery function in board_lateinit,merge the patch of ENGR00163704 Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00169654 mx53_pcba: enable DDR auto-calibrationRobin Gong2011-12-07-178/+620
| | | | | | | Enabled the functioon of DDR auto-calibration in flash_header.S of HW PCBA. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00169500 mc34708 mx53_loco: 4s power off in QS boardRobin Gong2011-12-06-0/+1
| | | | | | Implement the power off function when push the PWR key for 4s Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00163704: MX5X: add i2c recovery function in board_lateinit.Zhang Jiejing2011-12-05-0/+530
| | | | | | | | | | | | | | | | | | This patch add a i2c bus recovery function, the i2c bus busy because some device pull down the I2C SDA line. This happens when Host is reading some byte from slave, and then host is reset/reboot. Since in this case, device is controlling i2c SDA line, the only thing host can do this give the clock on SCL and sending NAK, and STOP to finish this transaction. To fix this issue: when we found SDA is low, we generate 8 clock to let device send data, then send a NAK, and STOP to finish this I2C transaction , after this the clock will be clean. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00163370 Android: uboot: mx53_smd fix warnning messageZhang Jiejing2011-11-29-2/+2
| | | | | | Fix minor error when adding recovery related code. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00163239-2 mc34708: enable extra charging circuitRobby Cai2011-11-28-0/+11
| | | | | | | | | current schema is to enable this extra charging circuit, and then enable or disable it by checking VBatt is less or more than 3.4v. If VBatt is less than 3.4v, enable it; otherwise disable it. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00163239-1 mc34708: fix not charging issue in ubootRobby Cai2011-11-28-3/+13
| | | | | | there's some incorrect setting in spi mode, fixed in this patch. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00162717 mx53_smd/mx53_loco DA9053: reset da9053 i2c and add dummy writeWayne Zou2011-11-25-66/+164
| | | | | | | | mx53_smd, mx53_loco DA9053: reset da9053 i2c by sending 9 dummy clock and start/stop when bootup and add dummy write when accessing da9053 registers. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00162709 Add Support for MX6Q Sabre AutoEric Sun2011-11-21-0/+1846
| | | | | | | 1. Change RAM size from 2GB to 1GB 2. Default boot from MMC Dev 2 Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00162491 Android: MX53_SMD: enter recovery mode by key.Zhang Jiejing2011-11-18-1/+16
| | | | | | | | | | | Implement a key press check on recovery mode check. User can press Vol- key to enter recovery mode when boot. Idealy, should be a combo key press together, but on SMD it only can Vol+ or Vol- but it can't press together. More usuful for user and less bug. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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