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* powerpc/t4240rdb: Add alternate SerDes 2 protocol to align with RCWChunhe Lan2015-01-16-1/+1
| | | | | | | | | SerDes 2 protocol 56 is not valid any longer due to the new RCW; protocol 55 is used instead, so add SerDes 2 protocol 55 to align with RCW. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t4rdb: Add alternate serdes protocols to align with A-007186Chunhe Lan2014-06-05-1/+1
| | | | | | | | | | | | | | | | | | A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols only using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. Alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: Add T4240RDB board supportChunhe Lan2014-05-13-0/+146
T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]