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* mpc85xx/t104xrdb : remove raw timing parametervijay rai2015-03-05-44/+0
| | | | | | | | This board uses DDR DIMM. Reading SPD provides more flexibility. Raw timing parameter code should be removed after debugging. Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/T1040rdb: Add VSC9953 support for T1040rdb boardCodrin Ciubotariu2015-01-21-0/+50
| | | | | | | | This patch configures and initializes the L2 switch on T1040rdb board. The external L2 switch ports may be connected to PHYs only over QSGMII, for T1040rdb. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
* board/T104xrdb: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYsCodrin Ciubotariu2015-01-21-2/+7
| | | | | | | | | | | | | Freescale's T1040qds board may be configured to have up to 5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports, 2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2), connected to other two ports from an intergrated VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link ports have no PHYs attatched, so they don't have a corresponding MDIO. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: SECURE BOOT- Add secure boot target for T1042RDBgaurav rana2015-01-16-0/+1
| | | | | | | Secure boot target is added for T1042RDB platform. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/t104xrdb: convert deep sleep to generic board interfaceTang Yuantian2014-12-15-29/+33
| | | | | | | | A new interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t104xrdb: Conditional workaround of errata A-008044Prabhakar Kushwaha2014-12-05-8/+14
| | | | | | | | | | Workaround of Errata A-008044 was implemented without errata number and it is enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0. So put errata number and make it conditional. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Put errata number for T104x NAND boot issuePrabhakar Kushwaha2014-12-05-2/+2
| | | | | | | | | | | | When device is configured to load RCW from NAND flash IFC_A[16:31] are driven low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using IFC_A[16:31] lines are not accessible. Workaround is already in-place. Put the errata number to adhere errata handling framework. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fdt: Allow ft_board_setup() to report failureSimon Glass2014-11-21-1/+3
| | | | | | | | | | | | | | | | | | This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfgPriyanka Jain2014-11-14-0/+10
| | | | | | | | | | | | | | | | | -A_007662 states that for x1 link width, PCIe2 controller trains in Gen1 speed while configured for Gen2 speed. Workaround:Set the width to x1 and speed to Gen2 by writing to CCSR registers in PBI phase -A_008007 states that PVR register may show random value. Workaround: Reset PVR register using DCSR space in PBI phase Add PBI based software workaround for A_007662 and A_008007 in t104x_pbi.cfg. This is required for SPL-based bootloaders like NAND-boot, SD-boot, SPI-boot Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-09-26-11/+42
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| * powerpc/t104xrdb: Set DDR ODT to 75ohmPriyanka Jain2014-09-24-5/+5
| | | | | | | | | | | | | | | | | | | | DDR-ODT require cfg_dram_type switch set properly as per DDR type. T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type should be set to OFF for DDR3L Update t104xrdb/README for switch setting Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t104xrdb: Add T1042RDB board supportvijay rai2014-09-24-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042RDB is a Freescale reference board that hosts the T1042 SoC (and variants). The board is similar to T1040RDB, T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). T1042RDB is configured with serdes protocol 0x86 which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 DTSEC1, DTSEC2 are not connected on board. This Patch - add T1042RDB support - updates README file for T1042RDB details and update commands for switching to alternate banks from vBank0 to vBank4 and vice versa This patch also does minor clean ups for fdt defines for T1042RDB and T1042RDB_PI board Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t104xrdb: Add Support of rcw for T1042RDB in u-bootvijay rai2014-09-24-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support of rcw for T1042RDB, it makes following changes : - Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB - Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates comments for valid serdes protocol which is 0x06 - Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | MAINTAINERS: comment out blank M: fieldMasahiro Yamada2014-09-24-1/+1
|/ | | | | | | | | | | | | | | | | | Since commit ddaf5c8f3030050fcd356a1e49e3ee8f8f52c6d4 (patman: RunPipe() should not pipe stdout/stderr unless asked), Patman spits lots of "Invalid MAINTAINERS address: '-'" error messages for patches with global changes. It takes too long for Patman to process them. Anyway, "M: -" does not carry any important information. Rather, it is just like a place holder in case of assigning a new board maintainer. Let's comment out. This commit can be reproduced by the following command: find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada2014-09-13-3/+0
| | | | | | | | | | | | | | | | | | Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/t104xrdb: support deep sleep in SPI/SD bootTang Yuantian2014-08-12-0/+19
| | | | | | | | | | | | Add deep sleep support in SPI/SD boot. The destination address second stage uboot image is loaded to is changed because currently this address will be used by kernel which means we can't reserve it for resume. Entry point to kernel is still placed in second stage uboot. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1042RDB: Add Video - HDMI supportJason Jin2014-08-12-0/+85
| | | | | | | | | | | | | | | | | | | | | | | T1042 has internal display interface unit (DIU) for driving video. T1042RDB supports video mode via -LCD using TI enconder -HDMI type interface via HDMI encoder Chrontel, CH7301C encoder which is I2C programmable is used as HDMI connector on T1042RDB. This patch add support to -enable Video interface for T1042RDB -route qixis multiplexing to enable DIU-HDMI interface on board -program DIU pixel clock gerenartor for T1042 -program HDMI encoder via I2C on board This patch refer to the upstream diu patch (337b0c52b3296f371d04aef71a833e09110e0e6b) for T1040qds. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> [York Sun: resolve conflict and move changes to T104xRDB.h] Reviewed-by: York Sun <yorksun@freescale.com>
* Add board MAINTAINERS filesMasahiro Yamada2014-07-30-0/+22
| | | | | | | | | | | | | | | | | | | | We have switched to Kconfig and the boards.cfg file is going to be removed. We have to retrieve the board status and maintainers information from it. The MAINTAINERS format as in Linux Kernel would be nice because we can crib the scripts/get_maintainer.pl script. After some discussion, we chose to put a MAINTAINERS file under each board directory, not the top-level one because we want to collect relevant information for a board into a single place. TODO: Modify get_maintainer.pl to scan multiple MAINTAINERS files. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* kconfig: add board Kconfig and defconfig filesMasahiro Yamada2014-07-30-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - arch/${ARCH}/Kconfig provide a menu to select target boards - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig set CONFIG macros to the appropriate values for each board - configs/${TARGET_BOARD}_defconfig default setting of each board (This commit was automatically generated by a conversion script based on boards.cfg) In Linux Kernel, defconfig files are located under arch/${ARCH}/configs/ directory. It works in Linux Kernel since ARCH is always given from the command line for cross compile. But in U-Boot, ARCH is not given from the command line. Which means we cannot know ARCH until the board configuration is done. That is why all the "*_defconfig" files should be gathered into a single directory ./configs/. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* powerpc/mpc85xx: Check return value of find_tlb_idxYork Sun2014-07-22-3/+9
| | | | | | | | | | find_tlb_idx() is called in board_early_init_r() on multiple boards. The return value is not checked before being used to disable a TLB. In normal case the return value wouldn't be -1. In case of a mis- configuration during porting to a new board, checking the return value may be helpful to reveal some user errors. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: Toggle deep sleep management signals after resumeTang Yuantian2014-05-16-0/+2
| | | | | | | | | T104xrdb has several sleep management signals that are used for deep sleep. They are enabled by OS to enter deep sleep and should be disabled by u-boot when cores wake up. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1040rdb: added a break in switch caseShaohui Xie2014-04-22-0/+1
| | | | | | | | There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it will fall into case PHY_INTERFACE_MODE_RGMII. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDBPrabhakar Kushwaha2014-04-22-3/+256
| | | | | | | | | | | | | | Add support of 2 stage NAND, SD, SPI boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: Add deep sleep support on T104xRDBTang Yuantian2014-04-22-0/+10
| | | | | | | Add deep sleep support on T104xRDB platforms. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t104xrdb: Add support of CPLDPrabhakar Kushwaha2014-04-22-0/+166
| | | | | | | | | | | T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: Update DDR initialization related settingsPriyanka Jain2014-03-07-28/+23
| | | | | | | | | | | | | | | | | | Update following DDR related settings for T1040RDB, T1042RDB_PI -Correct number of chip selects to two as t1040 supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Update ddr_raw_timing sructure corresponding to DIMM. -Set ODT to off. Typically on FSL board, ODT is set to 75 ohm, but on T104xRDB, on setting this , DDR instability is observed. Board-level debugging is in progress. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: Add basic ethernet supportPriyanka Jain2014-02-03-0/+73
| | | | | | | | | | | | | | | | | | | This covers only non-L2 switch ethernet interfaces i.e. RGMII and SGMII interface for both T1040RDB and T1042RDB_PI T1040RDB is configured as serdes protocol 0x66 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 1 SGMII on DTSEC3 T1042RDB_PI is configured as serdes protocol 0x06 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change in commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Fix README to show correct flash memory mapPrabhakar Kushwaha2014-02-03-3/+3
| | | | | | | | | | | | Due to increased size of u-boot, FMAN ucode start address has been shifted by 256KB causing a overlap with rootfs start address. Update rootfs start address to reflect correct memory map. Also fix minor typo in README Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Increase binary size for P, B & T series boards.Prabhakar Kushwaha2014-01-21-6/+6
| | | | | | | | | | | u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-2/+2
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: Add T1042RDB_PI board supportPriyanka Jain2013-11-13-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality T1042RDB_PI board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Two on-board RGMII 10/100/1G ethernet ports. - SERDES Connections, 8 lanes supporting: — PCI — SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Video - DIU supports video at up to 1280x1024x32bpp - HDMI connector - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* powerpc/t104xrdb: Add T1040RDB board supportPriyanka Jain2013-11-13-0/+650
T1040RDB is Freescale Reference Design Board supporting the T1040 QorIQ Power Architecture™ processor. T1040RDB board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: - PCI - SGMII - QSGMII - SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefile] Acked-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-01 21:49:11 +0000