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path: root/board/freescale/t102xrdb/ddr.c
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* powerpc: T1024RDB: Remove macro CONFIG_T1024RDBYork Sun2017-01-04-1/+1
| | | | | | | | Use TARGET_T1024RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Get missing hunk in board/freescale/t102xrdb/ddr.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* powerpc: T1023RDB: Remove macro CONFIG_T1023RDBYork Sun2017-01-04-1/+1
| | | | | | Use TARGET_T1023RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
* fsl/board/ddr: optimize board-specific cpo for erratum A-009942Shengzhou Liu2016-12-15-0/+4
| | | | | | | | | | Optimize board-specific cpo for erratum A-009942 on b4860qds, ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb, t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb, t4qds, t4rdb boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-06-04-2/+2
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| * board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl bootShengzhou Liu2016-06-03-2/+2
| | | | | | | | | | | | | | | | We should use unified setup_ddr_tlbs() for spl boot and non-spl boot to make sure 'M' bit is set for DDR TLB to maintain cache coherence. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | board/freescale: Update ddr clk_adjustShengzhou Liu2016-06-03-6/+6
|/ | | | | | | | | This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/t1023rdb: Add T1023 RDB board supportShengzhou Liu2015-05-04-1/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview ----------------------- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC card and eMMC on-board - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix defconfig files] Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/t102xrdb: convert deep sleep to generic board interfacetang yuantian2015-01-16-0/+19
| | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Besides, added SPI/SD/NAND boot deep sleep support. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1024rdb: Add T1024 RDB board supportShengzhou Liu2014-12-05-0/+154
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>