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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-60/+5
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/p2041: fix serdes reference clock frequency display for PC boardShaohui Xie2013-05-24-0/+11
| | | | | | | | | | PC board has different serdes clock setting with PB board, it uses same serdes frequency setting on bank2 as on bank1. PC board can be distingushed from PB board by checking CPLD version, if running on PC board, then fix the serdes reference clock frequency of bank2. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* ppc: Move lbc_clk and cpu to arch_global_dataSimon Glass2013-02-04-1/+1
| | | | | | | | Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Update for bsc9132qds.c, b4860qds.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/p2041: move Lanes mux to board early initShaohui Xie2013-01-30-39/+44
| | | | | | | | | | Lanes mux currently is configured in eth.c when initializing FMAN ethernet ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to p2041rdb.c which implements a board-specific initialization and will be called at early stage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p2041: configure the CPLD lane_mux according to RCWShaohui Xie2012-08-08-0/+39
| | | | | | | | | | | | | | | | | | | Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg is 0xc, CPLD supports SATA by default, we should re-configure the lane muxing according to RCW, which indicates what SerDes protocol it is running. Default lane muxing map is as below: Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg; Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg; Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2 and bit 3 respectively. Default value of these bits for lane muxing is '1', we should set or clear these bits accoring to RCW. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* doc: cleanup - move board READMEs into respective board directoriesWolfgang Denk2012-07-29-0/+123
| | | | | | | | | | | | | | | | Also drop a few files referring to no longer / not yet supported boards. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Jason Jin <jason.jin@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* powerpc/85xx: Add USB device-tree fixup for various platformsramneek mehresh2012-07-06-1/+5
| | | | | | | Add USB device-tree fixup for following platforms: MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during bootTimur Tabi2012-04-24-4/+0
| | | | | | | | | | | | | | | | Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* p2041rdb: fix serdes clock mapShaohui Xie2011-12-06-10/+15
| | | | | | | | | | | | | | | | | | Description of SerDes clock Bank2 setting in p2041 hardware specification is wrong, the clock map which based on it is wrong either, so fix the serdes clock map. wrong setting of SERDES Reference Clocks Bank2: SW2[5:6] = ON OFF =>100MHz for PCI mode SW2[5:6] = OFF ON =>125MHz for SGMII mode right setting of SERDES Reference Clocks Bank2: SW2[5:6] = OFF OFF =>100MHz for PCI mode SW2[5:6] = OFF ON =>125MHz for SGMII mode SW2[5:6] = ON OFF =>156.25MHZ Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/QorIQ: fix network frame manager TBI PHY address settingsRoy Zang2011-11-08-8/+0
| | | | | | | | | | | | TBI PHY address (TBIPA) register has been set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c So remove the duplicate code on QorIQ frame manager Ethernet related platforms, which include Hydra board, P4080DS board and P2041rdb board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* punt unused clean/distclean targetsMike Frysinger2011-10-15-6/+0
| | | | | | | | | | The top level Makefile does not do any recursion into subdirs when cleaning, so these clean/distclean targets in random arch/board dirs never get used. Punt them all. MAKEALL didn't report any errors related to this that I could see. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* powerpc/mpc8xxx: Merge entries in DDR speed tableYork Sun2011-10-09-28/+50
| | | | | | | | | | | | | | | It is not necessary to keep multiple entries for the same setting in DDR speed tables. Merge them for smaller tables. Also restructure the tables for smaller size. Cleanup some typedefs. Enforce strict checking for speed table. If DIMM is running at higher than known speed, try to use the highest speed setting. If rank is unknown, it has to panic. Removed ODT overriding for P2020DS as it is not necessary. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: remove watch dog related codesShaohui Xie2011-10-03-12/+1
| | | | | | | | | | CPLD 2.2 removed board watch dog support due to the limitation of CPLD capacity after adding all the requested features, such as switch overriding. There is no pin-compatible upgrade part available for current PCB design. So remove codes related to it. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: updated description of cpld commandShaohui Xie2011-10-03-8/+8
| | | | | | | | According to CPLD 2.2, the default configuration is changed, so updated the description of CPLD command, otherwise it will confusing. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: add more ddr frequencies supportShaohui Xie2011-10-03-1/+4
| | | | | | | | | This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833, 1000, 1066 and 1333 were verified on this board with SO-DIMM (UG51U6400N8SU-ACF). Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: set sysclk according to status of physical switch SW1Shaohui Xie2011-10-03-0/+17
| | | | | | | | | | | | | P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software need to read the SW1 status to decide what the sysclk needs. SW1[8~6] : frequency 0 0 1 : 83.3MHz 0 1 0 : 100MHz others: 66.667MHz Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: update cpld reset command according to CPLD 2.0Shaohui Xie2011-10-03-7/+11
| | | | | | | | | CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Refactor P2041RDB to use common p_corenet filesKumar Gala2011-09-29-202/+0
| | | | | | | | | | | The P2041RDB has almost identical setup for TLB, LAWS, and PCI with other P-Series CoreNet platforms. The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the TLB and LAW setup tables. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entriesKumar Gala2011-09-29-15/+19
| | | | | | | We shouldn't be setting execute permissions on TLB entries that will not actually have any code run from them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: Add ethernet support on P2041RDB boardMingkai Hu2011-09-29-0/+230
| | | | | | | | | | | | | | Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board. The five dTSEC can be routed to two on-board RGMII phy, three on-board SGMII phy or four SGMII phy on SGMII riser card according to different serdes protocol configuration and board lane configuration. Also updated the device tree to direct the Fmac MAC to the correct PHY. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8xxx: drop redundant boot messagesWolfgang Denk2011-07-29-1/+1
| | | | | | | | | | | | | | | Current code would print RAM size information like this: DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Turn a number of printf()s into debug() to get rid of the redundant "DDR: " string like this: DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: Add p2041rdb board supportMingkai Hu2011-07-17-0/+793
P2041RDB Specification: ----------------------- Memory subsystem: * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) * 128 Mbyte NOR flash single-chip memory * 256 Kbit M24256 I2C EEPROM * 16 Mbyte SPI memory * SD connector to interface with the SD memory card Ethernet: * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) PCIe: * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces I2C: * I2C1: Real time clock, Temperature sensor, Memory module * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2 UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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