arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	powerpc/85xx: Refactor P2041RDB to use common p_corenet files	Kumar Gala	2011-09-29	-123/+0
\| \| \| \| \| \| \| \| \| \| \|	The P2041RDB has almost identical setup for TLB, LAWS, and PCI with other P-Series CoreNet platforms. The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the TLB and LAW setup tables. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries	Kumar Gala	2011-09-29	-15/+19
\| \| \| \| \| \| \|	We shouldn't be setting execute permissions on TLB entries that will not actually have any code run from them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/p2041rdb: Add p2041rdb board support	Mingkai Hu	2011-07-17	-0/+119
	P2041RDB Specification: ----------------------- Memory subsystem: * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) * 128 Mbyte NOR flash single-chip memory * 256 Kbit M24256 I2C EEPROM * 16 Mbyte SPI memory * SD connector to interface with the SD memory card Ethernet: * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) PCIe: * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces I2C: * I2C1: Real time clock, Temperature sensor, Memory module * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2 UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>