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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/p2041: move Lanes mux to board early initShaohui Xie2013-01-30-39/+0
| | | | | | | | | | Lanes mux currently is configured in eth.c when initializing FMAN ethernet ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to p2041rdb.c which implements a board-specific initialization and will be called at early stage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p2041: configure the CPLD lane_mux according to RCWShaohui Xie2012-08-08-0/+39
| | | | | | | | | | | | | | | | | | | Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg is 0xc, CPLD supports SATA by default, we should re-configure the lane muxing according to RCW, which indicates what SerDes protocol it is running. Default lane muxing map is as below: Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg; Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg; Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2 and bit 3 respectively. Default value of these bits for lane muxing is '1', we should set or clear these bits accoring to RCW. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/QorIQ: fix network frame manager TBI PHY address settingsRoy Zang2011-11-08-8/+0
| | | | | | | | | | | | TBI PHY address (TBIPA) register has been set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c So remove the duplicate code on QorIQ frame manager Ethernet related platforms, which include Hydra board, P4080DS board and P2041rdb board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2041rdb: Add ethernet support on P2041RDB boardMingkai Hu2011-09-29-0/+225
Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board. The five dTSEC can be routed to two on-board RGMII phy, three on-board SGMII phy or four SGMII phy on SGMII riser card according to different serdes protocol configuration and board lane configuration. Also updated the device tree to direct the Fmac MAC to the correct PHY. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>