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* powerpc/85xx: Fix P2020DS bootingKumar Gala2011-10-18-0/+12
| | | | | | | | | | | | | The following commit removed the code that set odt_rd_cfg and odt_wr_cfg. With out this code P2020DS board will not boot: commit 712cf7ab0b58e51a69e339397457d3591b6b650e Author: York Sun <yorksun@freescale.com> Date: Mon Oct 3 09:19:53 2011 -0700 powerpc/mpc8xxx: Merge entries in DDR speed table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Merge entries in DDR speed tableYork Sun2011-10-09-49/+56
| | | | | | | | | | | | | | | It is not necessary to keep multiple entries for the same setting in DDR speed tables. Merge them for smaller tables. Also restructure the tables for smaller size. Cleanup some typedefs. Enforce strict checking for speed table. If DIMM is running at higher than known speed, try to use the highest speed setting. If rank is unknown, it has to panic. Removed ODT overriding for P2020DS as it is not necessary. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc85xx: Display a warning for unsupported DDR data ratesYork Sun2011-07-11-0/+6
| | | | | | | | If DDR initialziation uses a speed table and the speed is not matched, print a warning message instead of silently ignoring. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala2011-04-04-19/+0
| | | | | | | | | | | | | | Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala2011-04-04-5/+0
| | | | | | | | | | Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix parameters to support RDIMM for P2020DSYork Sun2010-08-31-2/+2
| | | | | Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2020ds: Integrated with P2020DS DDR change and enabled hwconfigyork2010-07-26-29/+27
| | | | | | | | Enabled SPD Enabled DDR2 Enabled hwconfig Signed-off-by: York Sun <yorksun@freescale.com>
* 85xx: Add P2020DS supportSrikanth Srinivasan2009-06-12-0/+130
The patch adds support for P2020DS reference platform. DDR3 interface uses hard-coded initialization rather than SPD for now and was tested at 667Mhz. Some PIXIS register definitions and associated code sections need to be fixed. TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all tested under u-boot. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>