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* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-72/+128
|\ | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPLYing Zhang2014-02-24-72/+128
|/ | | | | | | | | | | | | | | | | | | | | | In the previous patches, we introduced the SPL/TPL fraamework. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Increase binary size for P, B & T series boards.Prabhakar Kushwaha2014-01-21-8/+8
| | | | | | | | | | | u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* board/freescale:Remove use of CONFIG_SPL_NAND_MINIMALPrabhakar Kushwaha2014-01-02-1/+1
| | | | | | | | | CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary review purpose. So, use CONFIG_SPL_NAND_BOOT config. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-1/+1
| | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-25-1/+2
| | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-4/+4
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/p1010rdb: update readme for p1010rdb-pa and p1010rdb-pbShengzhou Liu2013-11-13-2/+190
| | | | | | | | | | - Remove duplicate doc/README.p1010rdb - Rename README to README.P1010RDB-PA - Add new README.P1010RDB-PB P1010RDB-PB is a variation of previous P1010RDB-PA board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* board: powerpc: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-25/+5
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de>
* powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-paShengzhou Liu2013-10-16-6/+170
| | | | | | | | | | | | - Rename old P1010RDB board as P1010RDB-PA. - Add support for new P1010RDB-PB board. - Some optimization. For more details, see board/freescale/p1010rdb/README. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix conflicts in boards.cfg] Acked-by: York Sun <yorksun@freescale.com>
* board/p1010rdb: add pin mux and sdhc support in any bootShengzhou Liu2013-10-16-20/+105
| | | | | | | | | | | | | | | | Since pins multiplexing, SDHC shares signals with IFC, with this patch: To enable SDHC in case of NOR/NAND/SPI boot a) For temporary use case in runtime without reboot system run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. b) For long-term use case set 'esdhc' in hwconfig and save it. To enable IFC in case of SD boot a) For temporary use case in runtime without reboot system run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. b) For long-term use case set 'ifc' in hwconfig and save it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/p1010rdb: remove unused cpld_showShengzhou Liu2013-10-16-35/+0
| | | | | | Function cpld_show() was for debug and not called, so clean it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain2013-10-16-13/+13
| | | | | | | | | | | Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* powerpc/p1010rdb: fix calculating ddr_freq_mhzShengzhou Liu2013-08-20-1/+1
| | | | | | | | There was a bug for calculating ddr_freq_mhz, it should be divided by 1000000 rather than 0x1000000. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-1/+1
| | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-101/+6
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI definePrabhakar Kushwaha2013-06-20-1/+1
| | | | | | | PCIe TLB should be created with CONFIG_PCI defined Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPLPrabhakar Kushwaha2013-06-20-1/+6
| | | | | | | | | e500v2 processor does not support 8K page size TLB entries. So create new TLB entry only during NAND SPL boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/p1010rdb:Add NAND boot support using new SPL formatPrabhakar Kushwaha2013-06-20-6/+165
| | | | | | | | | | - defines constants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot - remove nand_spl support for P1010RDB Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p1010rdb: Change flexcan compatible stringShengzhou Liu2013-05-02-1/+1
| | | | | | | | Change flexcan compatible string from "fsl,flexcan-v1.0" to "fsl,p1010-flexcan" to match the device tree. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* ppc: Move lbc_clk and cpu to arch_global_dataSimon Glass2013-02-04-6/+6
| | | | | | | | Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Update for bsc9132qds.c, b4860qds.c] Signed-off-by: Tom Rini <trini@ti.com>
* p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit)Matthew McClintock2012-08-23-3/+4
| | | | | | | | | | | There was an extra 0 in front of the value we were using to mask, remove it to improve the code. Also fix the value written to ddr_sdram_cfg to set the bus width properly to 16 bits Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Minor Coding Style Cleanup.Wolfgang Denk2012-07-22-3/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Minor Coding Style cleanupWolfgang Denk2012-07-10-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()York Sun2012-07-06-5/+5
| | | | | | | | We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER(). This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with encryption. Remove all _E entries from SVR list and CPU list. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/p1010rdb: add readme document for p1010rdbShengzhou Liu2012-07-06-0/+212
| | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/p1010rdb: update mux config of p1010rdb boardShengzhou Liu2012-07-06-12/+44
| | | | | | | | | On p1010rdb some signals are muxed for tdm/can/uart/flash. If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly, defaultly we keep spi chip selection to spi-flash instead of to tdm/slic and disable uart1 when not using flexcan, as well disable sdhc. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during bootTimur Tabi2012-04-24-5/+1
| | | | | | | | | | | | | | | | Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boardsYork Sun2012-04-24-3/+3
| | | | | | | | | P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: Make inclusion of USB device fixup conditionalRamneek Mehresh2011-11-08-0/+2
| | | | | | | | Include call to usb device-fixup only when CONFIG_HAS_FSL_DR_USB is defined for the platform - P1020RDB, P1010RDB, P1020-PC Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* punt unused clean/distclean targetsMike Frysinger2011-10-15-6/+0
| | | | | | | | | | The top level Makefile does not do any recursion into subdirs when cleaning, so these clean/distclean targets in random arch/board dirs never get used. Punt them all. MAKEALL didn't report any errors related to this that I could see. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* powerpc/85xx: Add basic support for P1010RDBPoonam Aggrwal2011-09-29-0/+765
Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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