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i.MX7D VDD_ARM/SOC standby voltage should be 0.95V,
adding 25mV margin, so set it to 0.975V;
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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i.MX7D TO1.2 uses same DDR script as TO1.0,
TO1.1 uses dedicated DDR script.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 527d57e02b05eb0166dcaa1929e46dd2357a8720)
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On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend
mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated.
When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards),
DDR data corruption occured, not able to decrease CKE delay, so we have to add extra
delay on all other signals to balance it.
DDR script needs to be fine-tuned according to this hardware change.
For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from
533Mhz to 400Mhz.
We uses TO1.1 script at default, and retains the TO1.0 script for reference.
Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name
Signed-off-by: Ye Li <ye.li@nxp.com>
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Porting all mx7d arm2 boards (mx7d 12x12 lpddr3, 12x12 ddr3,
19x19 ddr3, 19x19 lpddr2, 19x19 lpddr3) support from u-boot v2015.04.
Signed-off-by: Ye Li <ye.li@nxp.com>
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