| Commit message (Collapse) | Author | Age | Lines |
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Abstracted the CSF size in imximage from a hardcoded value to a config
setting CONFIG_CSF_SIZE. This configuration is only enabled for secure
boot.
Increased the size of the CSF default allocation to 0x4000. This size
covers the event the worst case of 4906-bits keys.
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Update the DDR script for i.MX7D 12x12 LPDDR3 ARM2 board and
i.MX7D 19x19 LPDDR3 ARM2 board to file "7D_lpddr3_0_3.ds5"
Updated items:
Changes DRAMTMG2 WR2RD from 7 to 8.
Compass link for this script:
http://compass.freescale.net/livelink/livelink?func=ll
&objid=233861153&objAction=browse&sort=name
Test results:
Passed overnight test on two MX7D 12x12 LPDDR3 ARM2 board
Passed overnight test on one MX7D 19x19 LPDDR3 ARM2 board
Signed-off-by: Ye.Li <B37916@freescale.com>
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On MX7D, boot rom can provide some boot information such as boot device,
arm freq, axi freq, etc. (see the structure below)
Offset Byte4 | Byte3 | Byte2 | Byte1
0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved
0x4 ARM core frequency(in Hz)
0x8 AXI bus frequency(in Hz)
0x0C DDR frequency(in Hz)
0x10 GPT1 input clock frequency(in Hz)
0x14 Reserved
0x18
0x1C
The boot information can be accessed by get the pointer at 0x1E8. This patch
changes the u-boot to use the new approach. When manufacture boot, the info
recorded is the actual SD port, not the failed device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The LPDDR3 intialization in plugin codes were missed to update in previous
DDR script upgrading.
So update the plugin codes to LPDDR3 script: 7D_lpddr3_0_2.ds5
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 1874cec3a70adde2ea911a9c155fb41c43ccab61)
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[The compass link for this script]
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153
&objAction=browse&sort=name
[Changes in the script]
This script enable MDLL, but make it much more margin for the unlock state .
[DDR stress test result]
2 boards run the memtester for 3 days, and passed.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 6fa6765b0dcdad8d414931e49edf6ba65a73d23a)
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[The compass link for this script]
http://compass.freescale.net/livelink/livelinkfunc=ll&objid=233861153
&objAction=browse&sort=name
[Changes in the script]
1. Change the DDR freq to 528Mhz.
2. Disable ddr phy dll, just force a dll output. IC suspects the dll
in ddr phy may unlock sometimes. The side-effect is we will lost the
ability to compensate the voltage/temperature change, so it may easy
to fail at H/L temperature.
[DDR stress test result]
3 boards involved the two days stress test by using memtester tool.
One board met a kernel oops after one day test. Other two pass the
two days test.
Compared to previous DDR script, the result is much positive.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 843c3c54af12cbf20e7bc912178e5a3628b78198)
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Add support for HAB "Check data" all bits set and clear
check functionality. Rename CHECK_DATA to CHECK_BITS_SET.
Flag=0 -> (*address & mask) == 0 | All bits clear
Flag=2 -> (*address & mask) == mask | All bits set
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 0836912ef7a53d1f3d65f95556a34d03b8d65399)
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To enable the EPDC feature:
1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings
in mx7d_12x12_lpddr3_arm2.h
2. cd <kernel_dir>/firmware/imx
3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin
4. cp epdc_splash.bin to [FAT partition on SD card]
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 414824dcb77a067213849d340cf92777e6546810)
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This commit 155fa9af95ac5be857a7327e7a968a296e60d4c8
"spi: mxc: fix sf probe when using mxc_spi"
introduces "board_spi_cs_gpio" function to discard gpio in
CONFIG_SF_DEFAULT_CS for spi flash.
Follow this rule to make imx boards work fine.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Enable 1.8V on PHY control, so that Gigabit PHY operation
can be functional.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit a17f1300a1b6d3b46a090baa84ba2fef104a1af6)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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We should use CONFIG_FSL_QSPI, but not CONFIG_QSPI
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Upgrade to upstream way, using power_init_board.
Add pfuze300 support.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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* Update DCD table for lpddr3 @400Mhz
* Boot kernel linux and run memtester for memory stress
memtester 1G 100000
Signedoff-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
(cherry picked from commit 7cbab5830d486733a691be104cbc2be494b00776)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The default u-boot reset is a internal WDOG reset (warm reset on i.MX6) which
does not have power and DDR reset. So the peripherals and DDR may meet problem.
When using the internal WDOG reset on i.MX7D ARM2 boards,
we meets two DDR issues:
1. On 12x12 ARM2, sometimes the system may hang in DCD because the DDRC Operating Mode
does not become to normal.
2. On 19x19 ARM2, the reset always brings system to USB download because the
DDR3 turns to unstable.
On the i.MX7D ARM2 board, the WDOG_B signal connects to POR_B or PMIC_PWRON. This gives
a chance to use a stronger reset. So in this patch, we set the IOMUX for WDOG_B pin and
enable WDOG_B signal output in WDOG WCR register.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 1192501c1fcf3b266eb22639a6bc93ac7c03b367)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add BSP codes, configuration head file and build target for
12x12 LPDDR3 ARM2 board with basic functions:
ENET, I2C, SD/eMMC/MMC, USB, LCD Splash screen, QSPI, ECSPI,
pfuze3000 PMIC.
Note: pmic and video is still not upstream way
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ac0d51ef07fdec880e6da318c08d521506640efa)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
boards.cfg
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