| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
|
|
| |
Fix the SW2MODE setting problem in power_init_board, which causes issue when wakeup source
is set in kernel for LPSR.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 35e62eb779ffcc5af32a6fff615549e536bf6cf4)
|
| |
|
|
|
|
|
|
|
|
| |
without this patch, the QoS setting will be lost after exit LPSR mode.
The patch moves the QoS setting into DDR setting group (in plugin mode), thus
when exit LPSR mode, QoS setting will be restored as well as DDR setting.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 0b217456375bace3fbe9a72c7e92a46dc1907277)
(cherry picked from commit 75790929c674eea2f867b86a7734127d4cd45dfc)
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
PFUZE3000_SW1AB_SETP()
Commit:894a4b4da7e2 add the voltage configuration macro that base on
the 0.1mV precision, and i.MX6UL/i.MX6ULL/i.MX7D use the macro as 1mV
prevision that cause the conversion are wrong, then some boards cannot
boot up in ldo bypass mode.
The patch just correct the usage of PFUZE3000_SW1AB_SETP().
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
To improve the performance, enable the bank interleave for LPDDR3. Update
the LPDDR3 settings to new script IMX7D_LPDDR3_533MHz_2GB_32bit_V2.0.ds5.
Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. Change to 0 for reserved bits.
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1
Test:
Passed stress test on one 19x19 lpddr3 arm2 and one 12x12 lpddr3 arm2.
Passed LPSR test on one 12x12 lpddr3 arm2.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 9a4fa3f8d2762791a76fd90e83feec8c8c9235b0)
|
|
|
Add mx7d 12x12 lpddr3 arm2 support, which has enabled the OF_CONTROL
and DM drivers
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
|
